Serial Addition: Locally Connected Architectures

Beiu, Valeriu; Aunet, Snorre; Nyathi, J.; Rydberg, Ray Robert; Ibrahim, Walid

doi:10.1109/tcsi.2007.907885

Cited by 20 publications

(10 citation statements)

References 124 publications

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“…8. Results for AVG are comparable with MAJ3 multiplexed full adders [40]. A clear benefit of 4LRA is also observed in this analysis.…”

Section: Design Space Exploration and Redundancy Analysissupporting

confidence: 75%

“…A standard CMOS (mirrored) 4-bit full adder consisting of 100 transistors is used as a unit, building a reliable block. Full adders are crucial in arithmetic operations and are often used as relevant circuits for reliability analysis including some new publications [40], [41]. The probability of failure for a reliable block implementing reliable techniques is shown in Fig.…”

Section: Design Space Exploration and Redundancy Analysismentioning

confidence: 99%

See 1 more Smart Citation

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Stanisavljević

Schmid

Leblebici

2009

IEEE Trans. Nanotechnology

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This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A faulttolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10 −5 ). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.Index Terms-Fault-tolerant architecture, high defect density, redundancy, reliability of nanoelectronic systems.1536-125X/$25.00

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“…8. Results for AVG are comparable with MAJ3 multiplexed full adders [40]. A clear benefit of 4LRA is also observed in this analysis.…”

Section: Design Space Exploration and Redundancy Analysissupporting

confidence: 75%

Section: Design Space Exploration and Redundancy Analysismentioning

confidence: 99%

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Stanisavljević

Schmid

Leblebici

2009

IEEE Trans. Nanotechnology

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“…This is a simpler scheme than the traditional R = 3 in combination with a voter, which has been discussed in [24], and is a low redundancy factor compared to all, or most, other existing schemes, including some mentioned in [7], [14]. Since serial addition has been proven to be more energy efficient than parallel, when running at the same speed, the serial adder is believed to be a better candidate than the parallel adder, for subthreshold arithmetics [15], [17]. The long and sleek structure should also make it more suitable for adding shorter wires (less capacitance and power) for shorted driven nodes and outputs, when combined with redundancy, compared to the large and almost quadratic form of the layout of the parallel adder.…”

Section: Discussionmentioning

confidence: 99%

“…Threshold gates, including minority-3 and majority-3 gates, may be sueful candidates for reliable future nano-circuits, according to [7], [14]. Serial addition may also be attractive for certain defect tolerant arithmetics [15], [16], [17], which motivated the inclusion of the 32-bit serial adder that are demonstrated by measurements.…”

Section: Introductionmentioning

confidence: 99%

Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS

Aunet

2009

2009 Norchip

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32-bit serial and parallel adders exploiting minority-3 elements and inverters only, are presented, including chip measurements. The implementation is done in a standard triplewell 90 nm CMOS process. Measurements also demonstrate that the digital abstraction may be maintained for basic building blocks under the presence of stuck-open faults and defect transistors, for a redundancy factor, R, of only 2. R = 2 combined with shorted driven nodes is lower than the traditional R=3 in combination with majority voting. For the serial adder the MSB as a result og toggling LSB in one of the 32-bit input words was adequately produced for 9 out of 10 prototype chips for a V dd of 250 mV, and for 5 prototypes when reduced to 200 mV. For the 32-bit parallel adder these numbers were 10 out of 10, and 4 out of 9 respectively. A new minority-3 gate is proposed, having a very regular layout, that could make it a suitable candidate for certain future nanocmos circuits. The energy effeciency for serial versus parallel adders, combined with the shape of their layout, may make them good candidates to be combinated with redundancy for ultra low power, subthreshold, defect-tolerant arithmetic circuits.

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“…Threshold [22] 300 mV 120 nm [25] gates offer dramatic reduction in the number of wires and interconnect when compared to traditional Boolean implementations [30]. Simulations and measurements have demonstrated circuits maintaining functionality despite up to several transistors not able to perform pull-up or pull-down, for redundancy factors down to only 2 [31], [16], [19] or 3 [32], when exploiting minority-3 gates with no voter and shorted outputs, as suggested in [22]. Serial addition have been shown to have less power-and energy consumption than parallell, when operating at the same computational speed, for example for 32 bits two's complement words [33].…”

Section: Building Blocksmentioning

confidence: 99%

On the reliability of ultra low voltage circuits built from minority-3 gates

Aunet

2011

2011 20th European Conference on Circuit Theory and Design (ECCTD)

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Different ultra low voltage implementations of the minority-3 function are compared with respect to robustness, area and metrics including power, energy and delay. It is shown how entire synchronous or asynchronous systems could be made from minority-3 functions only, instead of traditional Boolean gates and memory. Chip measurements and simulations in 120, 90 and 65 nm technologies are used as background. Monte Carlo simulations including process and parameter variations, as well as multi-objective optimization algorithm, are used to compare implmentations of combinatorial circuits and memory, based on Boolean gates and minority-3 gates. The most promising minority-3 implementations are suggested, for use in arithmetics and memory, like D-latches and Muller C elements. A brief discussion suggests implementation of arithmetics based on serial adders instead of parallell, as they have been shown to be more power-and energy-economic for the same computational throughput, under subthreshold operation. Low level redundancy, with a redundancy factor from 2 (duplication) and up, may be used for defect and error tolerance, using shorted driven outputs and no voter.

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Serial Addition: Locally Connected Architectures

Cited by 20 publications

References 124 publications

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Subthreshold minority-3 gates and inverters used for 32-bit serial and parallel adders implemented in 90 nm CMOS

On the reliability of ultra low voltage circuits built from minority-3 gates

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