On the reliability of ultra low voltage circuits built from minority-3 gates

Abstract

Different ultra low voltage implementations of the minority-3 function are compared with respect to robustness, area and metrics including power, energy and delay. It is shown how entire synchronous or asynchronous systems could be made from minority-3 functions only, instead of traditional Boolean gates and memory. Chip measurements and simulations in 120, 90 and 65 nm technologies are used as background. Monte Carlo simulations including process and parameter variations, as well as multi-objective optimization algorithm, are used to compare implmentations of combinatorial circuits and memory, based on Boolean gates and minority-3 gates. The most promising minority-3 implementations are suggested, for use in arithmetics and memory, like D-latches and Muller C elements. A brief discussion suggests implementation of arithmetics based on serial adders instead of parallell, as they have been shown to be more power-and energy-economic for the same computational throughput, under subthreshold operation. Low level redundancy, with a redundancy factor from 2 (duplication) and up, may be used for defect and error tolerance, using shorted driven outputs and no voter.