SERF and Modified SERF Adders for Ultra Low Power Design Techniques

Mohanraj, S.; Maheswari, M.

doi:10.1016/j.proeng.2012.01.909

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…O FA exato EXA faz uso de lógica de transistores de passagem (PTL -Pass-Transistor Logic), tendo sido elaborado com 10 transistores. Este circuito foi escolhido como exemplo de um circuito de baixa potência e eficiência em área para full adders [9] [10]. Como o circuito EMA CMOS, este dispositivo também tem a desvantagem de ser mais lento, devido à implementação PTL.…”

Section: Somadores Completosunclassified

Comparação de Topologias de Full Adders para Computação Aproximada

Meinhardt¹

2020

Anais Do XI Computer on the Beach - COTB '20

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This work provides an analysis of a set of approximate full addercircuits in 16nm CMOS device technology, with the goal of identifyinghow these designs behave in a specific environment andapplying voltage scaling when compared to conventional exactadders, focusing on reduction in power consumption. The resultsallow designers to evaluate the pros and cons of each design in errortolerant applications, especially in comparison with exact adders.In nominal tension, there was reduction of up to 90% in power consumptionin XNOR based inexact FAs, and up to 75% gain in powerand 25% gain in delay with CMOS simplifications. In near-thresholdvoltages, it was possible to obtain up to 22% improvement in delayand 50% in power consumption, when comparing the same designsoperating under nominal voltage. The best results were obtainedwhen applying voltage reduction in approximate designs, whichreached improvements in power of up to 98%.

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Section: Somadores Completosunclassified

Comparação de Topologias de Full Adders para Computação Aproximada

Meinhardt¹

2020

Anais Do XI Computer on the Beach - COTB '20

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“…According to requirement of applications these adders are used. Few full adder cells which are already implemented are conventional (10T) full adder cells [3][4][5][6], Static Energy Recovery Full adder cells (SERF) [7][8][9][10], Gate Diffusion Input (GDI) full adder Cells [11,12], etc. The Most complex computational circuit requires full adder circuitry hence the whole power consumption and speed of a computational circuit can be managed by implementing the low-power and high speed adder cell, so the overall performance of computational circuits totally depends on the adder cell.…”

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FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA

V.P¹

2023

IJTRET

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A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to simulate the schematic and layout as well as compare the schematic and layout for the purpose of determining precise design limitations. As part of this, we are going to perform the simulation of the CMOS full adder using T-SPICE of Tanner EDA and its layout design using the Microwind tool. The parameters such as power consumption, Area, Propagation Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed one-bit full adder

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Energy-Efficient Design of Approximated Full Adders

Silva

Meinhardt

2020

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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SERF and Modified SERF Adders for Ultra Low Power Design Techniques

Cited by 3 publications

References 10 publications

Comparação de Topologias de Full Adders para Computação Aproximada

Comparação de Topologias de Full Adders para Computação Aproximada

FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA

Energy-Efficient Design of Approximated Full Adders

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