Seqver : A Sequential Equivalence Verifier for Hardware Designs

Kaiss, Daher; Goldenberg, Silvian; Hanna, Ziyad; Khasidashvili, Zurab

doi:10.1109/iccd.2006.4380827

Cited by 7 publications

(4 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There has been much research on sequential equivalence checking (SEC) between RTL and gate-level hardware designs [33,34]. Research has also be done on combinational equivalence checking between high-level designs in software-like languages (e.g., SystemC) and RTL-level designs [11].…”

Section: Related Workmentioning

confidence: 99%

Formal Verification for High-Assurance Behavioral Synthesis

Ray

Hao

Chen

et al. 2009

Automated Technology for Verification and Analysis

View full text Add to dashboard Cite

Abstract. We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We show how to decompose this certification into two components, which can be respectively handled by the complementary verification techniques, theorem proving and model checking. The approach produces a certified reference flow, composed of transformations distilled from production synthesis tools but represented as transformations on graphs with an associated formal semantics. This tool-independent abstraction disentangles our framework from the inner workings of specific synthesis tools while permitting certification of hardware designs generated from a broad class of behavioral descriptions. We provide experimental results suggesting the scalability on practical designs.

show abstract

Section: Related Workmentioning

confidence: 99%

Formal Verification for High-Assurance Behavioral Synthesis

Ray

Hao

Chen

et al. 2009

Automated Technology for Verification and Analysis

View full text Add to dashboard Cite

show abstract

“…In the terminology of equivalence checking this means that not every state element in the RTL model needs to be mapped to a state element in the SCH model. Still, the equivalence checking method currently employed in RTL-to-SCH equivalence checking tools [11] requires that every memory cell in the two models be mapped, and each pair of mapped memory cells is verified for equivalence; the corresponding outputs in the two memories cannot be verified without using the memory cells as cut-points, to prune the cone of influence to a manageable size.…”

Section: Introductionmentioning

confidence: 99%

“…Recent advances in sequential equivalence checking [11], [2], [4] allow more freedom in memory design in the RTL, in that corresponding memories in RTL and SCH models need not be state-matching. That is, the differences between RTL and SCH memory designs can be in the number and placement of state elements, and not only in the implementation of Boolean logic.…”

Section: Introductionmentioning

confidence: 99%

Verifying equivalence of memories using a first order logic theorem prover

Khasidashvili

Kinanah

Воронков

2009

2009 Formal Methods in Computer-Aided Design

Self Cite

View full text Add to dashboard Cite

We propose a new method for equivalence checking of RTL and schematic descriptions of memories using translation into first-order logic. Our method is based on a powerful abstraction of memories and address decoders within them. We propose two ways of axiomatizing some of the bit-vector operations, decoders, and memories. The first axiomatization uses an algebra of operations on bit-vectors. The second axiomatization considers a bit-vector as a unary relation and memory as a relation of larger arity. For some designs, including real-life designs, the second axiomatization results in a first-order problem falling into a known decidable fragment of first-order logic and suitable for solving by modern first-order provers. Equivalence of real-life memories can be verified in seconds with our approach.

show abstract

“…There has also been significant work on SEC between RTL and gate-level hardware designs [14], [15]. Furthermore, there have been effort for SEC between software specifications and hardware implementations [16]: GSTE assertion graphs were extended so that an assertion graph edge has associated assignments that update state variables.…”

Section: Modular Analysismentioning

confidence: 99%

Optimizing equivalence checking for behavioral synthesis

Hao

Xie

Ray

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

View full text Add to dashboard Cite

Abstract-Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis. The optimizations exploit the high-level structure of the ESL description to ameliorate verification complexity. Experiments on representative benchmarks indicate that the optimizations can handle equivalence checking of synthesized designs with tens of thousands of lines of RTL.

show abstract

Seqver : A Sequential Equivalence Verifier for Hardware Designs

Cited by 7 publications

References 6 publications

Formal Verification for High-Assurance Behavioral Synthesis

Formal Verification for High-Assurance Behavioral Synthesis

Verifying equivalence of memories using a first order logic theorem prover

Optimizing equivalence checking for behavioral synthesis

Contact Info

Product

Resources

About