Sequential test generation based on real-valued logic simulation

Abstract

This paper presents an approach to the test generation for synchronous sequential circuits. This approach utilizes an extended logic simulation, called 7eal-valued logic simulation, and solves the sequential test generation problem as a kind of optimization problem. The approach has the possibility of high speed test generation, because high speed processing techniques, such as, vector processing, parallel processing, and so on, can be efficiently applied to the most time-consuming part of this approach. Experimental results for ISCAS'89 benchmark sequential circuits also illustrate the eficiency of this approach.

An enhanced fault model for high defect coverage

“…It has been shown experimentally that the SSAF multiple detection test pattern set (generated by real-valued simulation [5,6]) fails to detect a large number of SGLFH1s. The generated SGLFH1 test set achieves a high degree of fault coverage with a relatively small number of test patterns for physical surrogate faults if the circuit does not include multi-input gates.…”

“…The multiple detection test set for SSAFs was created by a real-valued simulation method [5,6] for a test pattern with n-fold (n = 1, 2, 5, 7, 10) detection of all SSAFs, excluding redundant faults. Generally the test pattern is generated by deterministic methods such as FAN, SOCRA-TES, and the like, but the real-valued simulation methods develop the test pattern by successively improving a random pattern and have the merit that the multiple detection test pattern can be changed easily by changing only the random pattern.…”

Full symbolic ATPG for large circuits

“…Most other work focussed on test generation for circuits without a reset state [9], [19], [17]. As already noted in [13], this is a dliffaxent problem and, though test generation may be harder, tagging, faults as undetectable may be easier.…”

On a logical fault model H1SGLF for enhancing defect coverage

“…A HISGLF test generator can be converted from a deterministic SSAF test generator by modifying the fault activation process to suit HISGLFs. In our experiments, we modified the realvalued logic simulalion based method [8] ATPG for a HlSGLF test generator. Some static compaction methods were also applied to 1 he ATPG.…”