1992
DOI: 10.1007/978-1-4615-3628-4
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Sequential Logic Synthesis

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Cited by 73 publications
(28 citation statements)
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“…In high-level very large scale integration (VLSI) design a DFA (actually finite state machines) is often used as the first implementation of a design and is mapped into sequential machines and logic [28]. Previous work has shown how a DFA can be readily implemented in RNN's and neural networks have been directly implemented in VLSI chips [60]- [62].…”
Section: Overview Of Papermentioning
confidence: 99%
“…In high-level very large scale integration (VLSI) design a DFA (actually finite state machines) is often used as the first implementation of a design and is mapped into sequential machines and logic [28]. Previous work has shown how a DFA can be readily implemented in RNN's and neural networks have been directly implemented in VLSI chips [60]- [62].…”
Section: Overview Of Papermentioning
confidence: 99%
“…The different types of encoding problems, studied in the past, are the finite state machine (FSM) state encoding problem and the input and the output encoding problem. Techniques for FSM state encoding have been discussed in [4,5,6,7,8,9,10]. The input encoding problem has been reported in [11,12].…”
Section: Introductionmentioning
confidence: 99%
“…In VLSI architectures, FSM decomposition is useful for a number of reasons. By controlling the topology and manner in which the machine is decomposed, it is possible to aim for an implementation with characteristics such as: high speed, as decomposition can usually lead to a reduction in logic depth [2]; low area, as state-encoding heuristics will often cope more efficiently with each of the smaller sub-FSMs than with the large lump-FSM [3]; reduction in interconnect complexity [4], and I/O minimization [5].…”
Section: Introductionmentioning
confidence: 99%
“…Decomposition strategies that partition the STG allow a wider solution space to be searched by the following phases of synthesis [2]. They proceed by breaking the STG into a number of sub-STGs, each containing an extra 'wait' state representing all states outside the sub-STG's domain.…”
Section: Introductionmentioning
confidence: 99%