An output encoding problem and a solution technique

Mitra, Subhasish; McCluskey, E.J.

doi:10.1109/43.766726

Cited by 6 publications

(3 citation statements)

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“…Constraint (23) guaranties that any pair of states, S j and S k , differ at least in one bit. Constraint (24) assigns the values of the outputs that are not don't care values, and thus they cannot be determined by the solver.…”

Section: Integer Linear Programming Formulationmentioning

confidence: 99%

“…Other techniques are focused on the optimal assignment of don't care outputs, which are very usual because the values of some outputs do not matter in some states. The technique called column compaction exploits these don't cares to reduce the number of logic functions that must be implemented [21][22][23][24][25]. The aim of this technique is to assign values of zero or one to the don't cares in order to achieve that two or more outputs are equal to each other, and so only one logic function must be implemented for each group of equivalent outputs.…”

Section: Introductionmentioning

confidence: 99%

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Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

Senhadji-Navarro

García-Vargas²

2023

Electronics

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This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation.

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Section: Integer Linear Programming Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

Senhadji-Navarro

García-Vargas²

2023

Electronics

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“…Output encoding is also the subject of [15]. This paper cites all the relevant works on the topic of encoding targeting logic minimization.…”

Section: I I R E L At E D W O R Kmentioning

confidence: 99%

Efficient Decompression of Binary Encoded Balanced Ternary Sequences

Müller

Prost-Boucle

Bourge

et al. 2019

IEEE Trans. VLSI Syst.

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A balanced ternary digit, known as a trit, takes its values in {-1, 0, 1}. It can be encoded in binary as {11, 00, 01} for direct use in digital circuits. In this correspondence, we study the decompression of a sequence of bits into a sequence of binary encoded balanced ternary digits. We first show that it is useless in practice to compress sequences of more than 5 ternary values. We then provide two mappings, one to map 5 bits to 3 trits and one to map 8 bits to 5 trits. Both mappings were obtained by human analysis and lead to boolean implementations that compare quite favorably with others obtained by tweaking assignment or encoding optimization tools. However, mappings that lead to better implementations may be feasible.

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