Sequential algorithm for low-power encoding internal states of finite state machines

Experiments on Minimization Method of Incompletely Specified Finite State Machines for Low Power Design

“…To estimate the efficiency of the offered method we used MCNC FSM benchmarks [14]. Each of tested FSM benchmarks was encoded using binary and one-hot encoding and sequential low power algorithm [13]. A power consumption estimation parameter was calculated using following values: output capacitance C = 3pF, frequency f = 5MHz, supply voltage V CC = 5V, input probability P(x i = 1) = 0,5.…”

“…In comparison to STAMINA the number of states is higher in 3 cases but the average reduction of the power consumption of the FSM makes 1.01 times, and on occasion (example train11) 1.25 times. The experimental results for encoding using the sequential low power algorithm [13] are presented in Table 3, where all parameters have the same meaning as in Table 1 and Table 2.…”

“…In the one-hot encoding only one bit of the code has '1' value and all other bits have '0' value. In addition, the sequential encoding algorithm for low power design [13] is proposed to use.…”

Synthesis Method of Finite State Machines Based on State Minimization for Low Power Design

“…After procedure of state minimization, the sequential algorithm of state assignment [12] is performed to provide encoding which minimizes the power consumption.…”

“…In the present paper, we propose a heuristic method for the minimization of incompletely specified FSMs that makes it possible to optimize a power consumption already at the stage of minimization of the number of internal states. In addition the method of synthesis also applies a special state assignment method called sequential encoding algorithm [12] designed for low power optimization. The proposed approach suits well for the implementation of FSMs on programmable logic devices (PLDs).…”