SEOS: Hardware Implementation of Real-Time Operating System for Adaptability

Ong, Soon Ee; Lee, Siaw Chen; Ali, Noohul Basheer Zain; Hussin, Fawnizu Azmadi

doi:10.1109/candar.2013.110

Cited by 34 publications

(23 citation statements)

References 10 publications

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“…One solution uses the EDF algorithm too but with the maximum number of tasks being only 64, 25 and the other approach uses priorities instead of deadlines, which is less e±cient for realtime systems in terms of CPU utilization. 26 There are other solutions based on priorities or static scheduling [27][28][29] as well. These solutions are suitable for systems consisting of hard real-time tasks only.…”

Section: Related Workmentioning

confidence: 99%

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

Kohútka

Nagy

Stopjaková

2019

J CIRCUIT SYST COMP

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This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.

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Section: Related Workmentioning

confidence: 99%

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

Kohútka

Nagy

Stopjaková

2019

J CIRCUIT SYST COMP

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“…We found that most of these solutions use the static RMS scheduling algorithm and some of them use EDF. They use architecture of task sorting based on multiplexer trees or FIFO structures which leads into issues with scalability [1][2][3][4][5][6].…”

Section: Related Workmentioning

confidence: 99%

Hardware Accelerated Scheduling in Real-Time Systems

Kohútka¹,

Vojtko

Krajcovic

2015

2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems

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There are two groups of task scheduling algorithms in real-time systems. The first group contains algorithms that have constant asymptotic time complexity and thus these algorithms lead to deterministic task switch duration but smaller theoretical CPU utilisation. The second group contains complex algorithms that plan more efficient task sequences and thus the better CPU utilisation. The problem is that each task scheduling algorithm belongs to one of these two groups only. This is a motivation to design a real-time task scheduler that has all the benefits mentioned above. In order to reach this goal, we decided to reduce the time complexity of an algorithm from the second group by using hardware acceleration. We propose a scalable hardware representation of task scheduler in a form of coprocessor based on EDF algorithm. Thanks to the achieved constant time complexity, the hardware scheduler can help real-time systems to have more tasks that meet their deadlines while keeping high CPU utilisation and system determinism. Another advantage of our task scheduler is that any task can be removed from the scheduler according to the ID of the task, which increases expandability of the task scheduler.

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“…Several hardware architectures designed for data sorting or implementation of MIN/MAX queues have been developed so far. However, they all suffer from consuming too many LUT (Look-up Tables) resources and they have relatively high chip area costs in ASIC (in addition to FPGA) technologies as well [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28].…”

Section: Introductionmentioning

confidence: 99%

Novel efficient on-chip task scheduler for multi-core hard real-time systems

Kohútka

Stopjaková

2020

Microprocessors and Microsystems

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This article presents an efficient hardware architecture of EDF-based task scheduler, which is suitable for hard real-time systems due to the constant response time of the scheduler. The proposed scheduler contains a queue of ready tasks that is based on a new MIN/MAX queue architecture called Heap Queue, which is inspired by Shift Registers, Systolic Arrays, heapsort algorithm, the Rocket Queue architecture and dualport RAMs. The instructions of the proposed scheduler have throughput of one instruction per two clock cycles regardless of the actual number of tasks managed by the scheduler, and regardless of the scheduler capacity. The developed task scheduler is optimized for low chip area costs, which leads to lower energy consumption. The Heap Queue-based architecture has constant time complexity due to two clock-cycle response time of the instructions and therefore, the architecture is highly deterministic. The scheduler supports CPUs that can execute 1, 2 or 4 tasks simultaneously, and contains an implementation of clever and efficient logic that can handle conflicts caused by the fact that the scheduler is used by all CPU cores at the same time. The proposed scheduler was verified through SystemVerilog UVM-like simulations that applied billions of randomly generated test instructions. Achieved ASIC (28 nm) and FPGA synthesis results are presented and compared. More than 86% of the chip area and 93% of the total power consumption can be saved if Heap Queue architecture is used in hardware implementations of EDF algorithm. Advantages and disadvantages of the proposed task scheduler are discussed through the comparison to the existing solutions.

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SEOS: Hardware Implementation of Real-Time Operating System for Adaptability

Cited by 34 publications

References 10 publications

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems

Hardware Accelerated Scheduling in Real-Time Systems

Novel efficient on-chip task scheduler for multi-core hard real-time systems

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