Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture

Hihara, Hiroki; Iwasaki, Akira; Hashimoto, Masanori; Ochi, Hiroyuki; Mitsuyama, Yukio; Onodera, Hidetoshi; Kanbara, Hirohisa; Wakabayashi, Keiji; Sugibayashi, Toshio; Takenaka, Takashi; Hada, H.; Tada, Munehiro; Miyamura, Miharu; Sakamoto, Toshitsugu

doi:10.1109/les.2018.2797064

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…Functions those cannot satisfy the latency requirement by software processing on an MCU are reinforced by FPGAs or other processing elements. We have established four-layered design frameworks 11,12 to assemble these processing elements. The design framework can also be applied to reliability and safety design…”

Section: Layered Design Framework Of Heterogeneous Edge Nodementioning

confidence: 99%

“…We encompassed the coarse grained layer and the fine grained layer as the scope of high-level synthesis to exploit the functional representations of circuitries. The following six steps compose a design flow using the four-layered architecture 11,12 . We use CyberWorkBench (CWB) 13,14,15 for high-level/behavioral synthesis.…”

Section: Pe Design With the Four-layered Design Frameworkmentioning

confidence: 99%

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Sensor electronics design framework with heterogeneous computing edge nodes

Hihara,

Imazato,

Yamaji

et al. 2023

Infrared Remote Sensing and Instrumentation XXXI

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Onboard sensor electronics of satellites are hard real-time systems and exploit high performance of heterogeneous computing. This paper describes sensor electronics design framework with heterogeneous computing edge nodes based on onboard demonstration records of satellites. Dedicated functional processing elements (PEs) for specific purposes implemented on Field Programmable Gate Arrays (FPGAs) and Application Specific Integration Circuit (ASIC) are used in addition to conventional Micro-Processing Units (MPUs). Many core processors like General Purpose Graphics Processing Units (GPGPUs) are also used for signal processing of sensor electronics in these days. Semiconductor process shrink is accelerating this technological trend. Because it reduces power consumption, size and mass while maintaining high processing performance. The applications of artificial intelligence, such as image recognition, became common for onboard sensor electronics. Dedicated PEs for image recognition implemented on FPGAs enables wire rate processing. Sensor signals are processed without interrupting data flow, and in-situ measurement results can be used for other purposes such as optical guidance and navigation. Heterogeneous computing edge nodes are often realized with distributed memory system. In addition to that the semantic gap between hardware and application software is widening. Despite these complexities, changes to the operation scripts of onboard sensor electronics are often needed on orbit. We have found that the layered architecture of heterogeneous PEs and the middle-out approach of system integration design are practical enough for onboard operation to aim at realizing user-centric command operation scripts. The design scheme is explained in this paper.

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Section: Layered Design Framework Of Heterogeneous Edge Nodementioning

confidence: 99%

Section: Pe Design With the Four-layered Design Frameworkmentioning

confidence: 99%

Sensor electronics design framework with heterogeneous computing edge nodes

Hihara,

Imazato,

Yamaji

et al. 2023

Infrared Remote Sensing and Instrumentation XXXI

Self Cite

View full text Add to dashboard Cite

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“…Sensor routers play a crucial role in the sector of Internet of Things (IOT) applications, in which the capacity for transmission of the network signal is limited from cloud systems to sensors and its reversal process. Consequence to this volume of the data reduction is obligatory to combat device computing functions between sensor nodes and transmitter to exchange the sufficient data with the available networks [1][2][3]. Hence, low power consumption and small footprints are commanded among sensor nodes to process information.…”

Section: Introductionmentioning

confidence: 99%

Sensor Signal Processing using High-Level Synthesis and Internet of Things with a Layered Architecture

Reddy¹,

Anand²

2022

IJANS

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Sensor routers play a crucial role in the sector of Internet of Things applications, in which the capacity for transmission of the network signal is limited from cloud systems to sensors and its reversal process. It describes a robust recognized framework with various architected layers to process data at high level synthesis. It is designed to sense the nodes instinctually with the help of Internet of Things where the applications arise in cloud systems. In this paper embedded PEs with four layer new design framework architecture is proposed to sense the devises of IOT applications with the support of high-level synthesis DBMF (database management function) tool.

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