Sensor electronics design framework with heterogeneous computing edge nodes

Abstract

Onboard sensor electronics of satellites are hard real-time systems and exploit high performance of heterogeneous computing. This paper describes sensor electronics design framework with heterogeneous computing edge nodes based on onboard demonstration records of satellites. Dedicated functional processing elements (PEs) for specific purposes implemented on Field Programmable Gate Arrays (FPGAs) and Application Specific Integration Circuit (ASIC) are used in addition to conventional Micro-Processing Units (MPUs). Many core processors like General Purpose Graphics Processing Units (GPGPUs) are also used for signal processing of sensor electronics in these days. Semiconductor process shrink is accelerating this technological trend. Because it reduces power consumption, size and mass while maintaining high processing performance. The applications of artificial intelligence, such as image recognition, became common for onboard sensor electronics. Dedicated PEs for image recognition implemented on FPGAs enables wire rate processing. Sensor signals are processed without interrupting data flow, and in-situ measurement results can be used for other purposes such as optical guidance and navigation. Heterogeneous computing edge nodes are often realized with distributed memory system. In addition to that the semantic gap between hardware and application software is widening. Despite these complexities, changes to the operation scripts of onboard sensor electronics are often needed on orbit. We have found that the layered architecture of heterogeneous PEs and the middle-out approach of system integration design are practical enough for onboard operation to aim at realizing user-centric command operation scripts. The design scheme is explained in this paper.