Sensitivity to Neutron Radiation of a 45 nm SOI Multi-Core Processor

Ramos, Pablo; Vargas, Vanessa; Baylac, M.; Villa, Francesca; Rey, Solenne; Clemente, Juan Antonio; Zergainoh, Nacer-Eddine; Velazco, Raoul

doi:10.1109/radecs.2015.7365665

Cited by 3 publications

(3 citation statements)

References 9 publications

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“…The validation of the proposed approach was done by SWIFI, which is a useful technique to emulate SEU effects. The adopted approach was proven in our previous works concerning fault-injection for multi-core processors [7,[37][38][39]. It is important to note that the objective of this approach is to reproduce the SEUs effects, which are bit-flips in memory cells caused by natural radiation.…”

Section: Resultsmentioning

confidence: 99%

“…The fault-injection technique proposed in this approach to emulate SEU is an SWIFI technique. As was previously stated, the approach validated in our previous works concerning fault-injection on multi-core processors [7,[37][38][39] is based on Code Emulated Upset (CEU) principles [47], which reproduce, without intrusion, the effects of SEUs. This is achieved by the assertion of asynchronous interrupt signals.…”

Section: Fault-injection Detailsmentioning

confidence: 99%

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NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

et al. 2018

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The N-Modular Redundancy and M-Partitions (NMR-MPar) fault-tolerance approach can be used to improve the reliability of embedded systems that are based on Commercial-Off-The-Shelf (COTS) multi-/many-core processors, especially those with a non-critical time constraint allowing a diminution in performance to gain reliability by maintaining power consumption. Typically, mixed-criticality systems, such as avionics or spacecraft, comply with these requirements.

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Section: Resultsmentioning

confidence: 99%

Section: Fault-injection Detailsmentioning

confidence: 99%

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

et al. 2018

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“…A preliminary version of this work was presented in [7]. The present work provides a detailed description of the adopted approach, the results regarding the errors not detected by the studied multi-core architecture, and a deep analysis of the experimental results including the probable causes of the observed errors.…”

Section: Introductionmentioning

confidence: 99%

Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons

Ramos

Vargas

Baylac

et al. 2016

IEEE Trans. Nucl. Sci.

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Abstract-The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.

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