NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

Vargas, Vanessa; Ramos, Pablo; Méhaut, Jean‐François; Velazco, Raoul

doi:10.3390/app8030465

Cited by 18 publications

(15 citation statements)

References 37 publications

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“…To mention relevant works, Shye et al (2009) proposed Process-Level Redundancy (PLR), a software layer running on the top of the operating system, automatically managing process triplication and their synchronized execution. Vargas et al (2018) proposed an approach to improve the reliability of NoCbased multi/many-core architectures. In particular, NMR is used to achieve fault tolerance, and replicas are distributed on isolated partitions to guarantee that no faulty replica contaminate the execution of any other replica.…”

Section: Error Detection and Recoverymentioning

confidence: 99%

On-Chip Dynamic Resource Management

Miele

Kanduri²,

Moazzemi³

et al. 2019

FNT in Electronic Design Automation

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The need for dynamic resource management has shadowed the exponential growth of on-chip transistor capacity, and the challenge is accentuated by the heterogeneity of resources, and the bewildering variety of constraints and requirements of applications, platforms and users. The field has started with a few research papers in the early 1990s but has grown today to over hundred yearly publications, leading to an accumulated body of literature presumable far above 1000 papers. We focus on the dynamic (run-time) management of onchip resources and mostly ignore design-time techniques and off-chip resources of larger electronic systems. Moreover, we do not attempt a complete review of all published work on the topic. Rather, this survey provides a structured review and discussion of the state of the art and is divided along the primary objectives of resource management techniques: performance, power, reliability and quality of service, each

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Section: Error Detection and Recoverymentioning

confidence: 99%

On-Chip Dynamic Resource Management

Miele

Kanduri²,

Moazzemi³

et al. 2019

FNT in Electronic Design Automation

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“…Table 2 summarizes the characteristics of both applications. The present work evaluates under neutron radiation the same case study implemented and evaluated by fault-injection in our previous work [18]. During neutron radiation tests, all sensitive areas summarized in Table 1 were assessed, but not the whole capacity of each area.…”

Section: = × (1)mentioning

confidence: 99%

“…Complementary, partitioning protects against not authorized access and data modification by temporal and spatial isolation of each partition. The proposed approach was presented in a previous work [18].…”

Section: Fault-tolerance Approachmentioning

confidence: 99%

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Evaluation by Neutron Radiation of the NMR-MPar Fault-Tolerance Approach Applied to Applications Running on a 28-nm Many-Core Processor

2018

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Currently, there is a special interest in validating the use of Commercial-Off-The-Shelf (COTS) multi/many-core processors for critical applications thanks to their high performance, low power consumption and affordability. However, the continuous shrinking of transistor geometry and the increasing complexity of these devices dramatically affect their sensitivity to natural radiation, and thus diminish their reliability. One of the most common effects produced by natural radiation is the Single Event Upset which is the bit-flip of a memory content producing unexpected results at application-level. For this reason, manufacturers and users implement hardware and software error-mitigation techniques on multi/many-core processors. In this context, the present work aims at evaluating a new fault-tolerance approach based on N-Modular redundancy (NMR) and partitioning called NMR-MPar by means of 14 MeV neutron radiation ground testing in order to emulate the effects of high-energy neutrons present at avionics altitudes. For evaluation purposes, a case-study is implemented on the 28 nm CMOS KALRAY MPPA-256 many-core processor running two complementary benchmarks applications: a distributed Matrix Multiplication and the Travel Salesman Problem. Radiation experiments were conducted in GENEPI2 particle-accelerator. The correctness of the results of the application when an error is detected confirms the approach’s effectiveness and boosts their usage on avionics applications.

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“…A bit-flip in the storage elements, including D flipflops (DFFs) and various types of memory, has different impacts on the vision processor performance. Directly hardening the vision processor via mitigation techniques [10,11,12] will lead to an extra chip area and power consumption. So we should initially evaluate the SEU sensitivity of the storage elements and identify the critical elements.…”

Section: Introductionmentioning

confidence: 99%

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors

Zhang

et al. 2019

IEICE Electron. Express

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This paper proposes novel single event upset (SEU) failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. To automatically evaluate the SEU failure probability and identify all the critical elements in a processor, complementary fault injection methods based on logic circuit simulator and Perl script are proposed. These methods can be used to randomly inject faults into D flip-flops (DFFs) and various types of memory at the register transfer level (RTL) as well as to evaluate the vision processor performance. Based on the evaluation results, an accurate periodic scrubbing technique is proposed to increase the processor availability. The results denote that the peak availability of the processor over a period of one year can be improved from 18% to 99.9% after scrubbing the RISC program memory for a period of 10 4 s. Therefore, we can improve the fault-tolerance performance of a vision processor while avoiding unnecessary area and power costs using techniques ranging from evaluation to mitigation.

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NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

Cited by 18 publications

References 37 publications

On-Chip Dynamic Resource Management

On-Chip Dynamic Resource Management

Evaluation by Neutron Radiation of the NMR-MPar Fault-Tolerance Approach Applied to Applications Running on a 28-nm Many-Core Processor

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors

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