Sensitive volume and triggering criteria of SEB in classic planar VDMOS

Abstract

this paper presents 2D numerical simulation results allowing to define the sensitive volume and triggering criteria of SEB for VDMOS of classic planar-type technology. The results analysis permits besides to better understand the SEB mechanism.

Single-Event Burnout Hardened Structure of Power UMOSFETs With Schottky Source

“…The generation rate of the created charges is described by spatial and temporal Gaussian functions. Considering that the linear energy transfer (LET) is unchanged in a certain range, we choose LET which is constant along the ionizing track so as to facilitate the study and the result interpretation [14], [30]. The hypothetical ion fully penetrates the device.…”

“…Many researchers have attempted to discuss the SEB characterization in power MOSFETs with a buffer layer [11], [12]. Then, the effects of ion species [13] and the sensitive volume for SEB performance of power MOSFETs have been discussed in detail [14], [15]. The research and exploration of SEB in power MOSFETs have been continued in recent years [16], [17], and 2-D simulators are used to investigate SEB performance [18], [19].The time evolution of SEB and the evaluation on protective SEB test method of power MOSFET have also been discussed [20], [21].…”

Tolerance Against Terrestrial Neutron-Induced Single-Event Burnout in SiC MOSFETs

“…Whereas, the typical thickness of N-drift layer of Si MOSFET is about m. And, the energetic secondary carbon atoms are higher linear energy transfer (LET) than that of the alpha particles. Therefore, the secondary carbon atoms may cause SEB in SiC power devices [23].…”

Single-Event Burnout Hardening of Power UMOSFETs With Optimized Structure

“…The generation rate of the created charges is described by spatial and temporal Gaussian functions. Considering that the LET is unchanged in a certain range, we choose LET that is constant along the ionizing track to facilitate the research and the result interpretation [11], [15]. The hypothetical ion fully penetrates the device.…”

“…Liu et al [12] showed an approach to properly design a buffer layer to maximize the device's SEB performance (to achieve the highest operating voltage under heavy ion environment), using quasi-stationary avalanche simulations and the effects of ion species on SEB failure voltage of power diffused MOSFET (DMOSFET) are also discussed [13]. The sensitive volume using 2-D numerical simulations for SEB performance of power MOSFETs is defined [14], [15]. Power transistors are widely used in space and atmospheric applications and many hardening solutions to SEB of power DMOSFETs were extensively investigated and tested these years.…”