Semiconductors at cryogenic temperatures

Jonscher, A. K.

doi:10.1109/proc.1964.3296

Cited by 50 publications

(13 citation statements)

References 59 publications

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“…In doped bulk silicon, the free-carrier mobility is expected to drop when transitioning below a certain cryogenic temperature and Coulombic impurity scattering becomes dominant over phonon scattering, leading to a typical bell-shaped mobility trend with respect to temperature [38,5] This behavior can be different in MOSFET devices when the channel is ballistic.…”

Section: Free-carrier Mobilitymentioning

confidence: 99%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

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This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physicsbased cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.The birth of CMOS-compatible qubits in silicon [1,2,3,4] has rebooted the interest in cryogenic CMOS electronics for computing applications. Since the 1970s, MOSFET devices have been under investigation at cryogenic temperatures for use in custom applications, such as low-noise scientific equipment, spacecraft, power conversion etc. [5,6,7,8,9]. However, despite its many benefits for reaching high-performance and low-power computing [10], cryogenic cooling did not stay into practice for computing, abandoning the trend set by the ETA-10 liquid-nitrogen-cooled supercomputer [11].Nowadays, co-integrating qubits and CMOS circuits on the same substrate can greatly aid the development of scalable quantum computers featuring massive parallelism and error correction [12,13,14]. In this context, a silicon-on-insulator (SOI) platform is particularly attractive since the back gate provides additional control over the electron-spin qubit, trapped under the front gate of a SOI (nanowire) MOSFET[12,15,16]. To integrate the control circuits with quantum devices working at deep-cryogenic temperatures, regular SOI MOSFETs need to demonstrate reliable digital, analog and RF functionalities at such low temperatures. Using SOI cryogenic control electronics, the back gate can prove a useful tool to control the threshold voltage and hence the power consumption in circuits integrated close to the qubits [17], benefiting qubit coherence time by lowering generated noise. The main focus is on advanced ultra-thin body fully-depleted SOI (FDSOI) technology, e.g., the 28-nm node, to enable ultimate scalability of the resulting hybrid quantum-classical system [16,18].The 28-nm node, presently considered the ideal node for analog and RF applications at room temperature [19], has recently been tested for digital and analog functionality down to liquid-helium temperature (4.2 K) [17], and millikelvin temperature (20 mK) [20]. The improvement in RF characteristics has been verified down to liquid-nitrogen temperature (77 K) [21]. In addition to device c...

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Section: Free-carrier Mobilitymentioning

confidence: 99%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

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“…In thermal equilibrium, the occupation of all electronic levels, both free and localized, is determined by the Fermi-Dirac distribution function Jonscher, 1964 …”

Section: Neutral Regionmentioning

confidence: 99%

Cryogenic Operation of Silicon Power Devices

Singh¹,

Baliga²

1998

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“…This would explain the reduced amplitude compared to room temperature. Under cryogenic conditions, the specific heat is reduced by four orders of magnitude resulting in a high increase in temperature at low power dissipation [6]. The band gap energy of silicon is increased from 1.12 eV to 1.19 eV at 6 Kelvin, which results in a higher value for the mid value to excite an electron-hole pair from 3.6 eV to 3.8 eV.…”

Section: Input Characteristicsmentioning

confidence: 99%

Investigation of single pixel DePMOSFETs under cryogenic conditions

Fedl¹,

Lütz²,

Strüder³

2008

2008 IEEE Nuclear Science Symposium Conference Record

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The observation of astrophysical objects in the midinfrared requires Blocked Impurity Band (BIB) detectors based on n-doped Silicon. Because of the low binding energy of the shallow impurities (42 meV to 54 meV), infrared radiation in the electromagnetic spectrum of 10 to 40 microns can excite electrons from the shallow impurities into the conduction band. To ensure the occupation of these impurities and to prevent high leackage current the Bm detector has to be cooled down to 5 K to 10 K. It is desirable to observe faint astronomical objects with such a detector, which can be achieved with a high Signal to Noise ratio. One possibility is an implemented DePMOSFET [1] on the Bm detector in order to be free of interconnection stray capacitance. We investigate the DePMOSFET at a temperature scale from 300 K down to 5 K. We show first results of characteristic and dYnamic measurements of the single pixel DePMOSFET at low temperature. We irradiate the single pixel with a 55Fe source and take a spectrum of the K a -and K B -line. The clear mechanism is investigated at temperatures lower than 50 K. The aim is a BIB detector based on an integrated amplifier with the DePMOSFET as a promising candidate.

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Semiconductors at cryogenic temperatures

Cited by 50 publications

References 59 publications

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Cryogenic Operation of Silicon Power Devices

Investigation of single pixel DePMOSFETs under cryogenic conditions

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