Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits

Guo, Jiun-In; Cao, Peng; Li, Mengxiao; Gong, Yu; Liu, Zhiyuan; Bai, Geng; Yang, Jun

doi:10.1109/tcad.2020.3015443

Cited by 3 publications

(7 citation statements)

References 25 publications

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“…The competitive model from [7] neglects the statistical impact to boundary between the fast and slow input slew, resulting in over-optimistic estimation for delay variation. As for [8], the transitional region is considered to be across the 3σ region of gate delay around τ b , leading to over-pessimistic estimation. Figure 7 shows the error results of different models of INV 5 fF.…”

Section: Resultsmentioning

confidence: 99%

“…The boundary to distinguish fast and slow input slew can be derived with Equation ( 4) by letting td equals τ/2, as given in Equation (8). It can be seen that τ b is proportional to td 0 and the proportion factor is independent with C L and W/L.…”

Section: Timing Variation Model For Input Slew In Transitional Regionmentioning

confidence: 99%

“…Many research works have been devoted to the subthreshold timing model for gate delay considering process variation [4][5][6][7][8][9][10][11][12][13], which revealed the relation between the delay and the variation sources analytically with physical insights. A fast delay estimation framework via fan-out-4 metric was proposed by [4] to evaluate the max delay variability causing by process variation across multiple PVT (Process-Voltage-Temperature) corners.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, more attention has been paid to the impact of slew time in delay model. A statistical subthreshold timing model was established in [7] by deriving gate delay variation analytically for the cases of fast and slow input slew separately, which was further optimized in [8] to improve the accuracy near the boundary of fast and slow input slew. Based on the assumption that the gate delay follows lognormal distribution, the statistical gate delay models were established analytically in [9,10] for inverter and complex gates to derive the delay mean value and its standard deviation considering process variations.…”

Section: Introductionmentioning

confidence: 99%

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Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Cao

et al. 2023

Electronics

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Subthreshold design provides the promising advantage of low power consumption at the cost of performance variation and even circuit failure. An accurate and efficient statistical timing model is crucial for timing analysis and performance optimization guidance. Prior works lack the consideration of the impact of slew time or the transitional region for input slew due to process variation and efficient approaches considering the impact of load capacitance and multiple process variations in complex gates, resulting in accuracy loss. In this work, an accurate end efficient gate delay variation model is analytically derived for various input slews and load capacitances. The transitional region between fast and slow input slew is efficiently partitioned with an adaptive error tolerance method so as to characterize timing variation by linear interpolation based on that for fast and slow input slew. In order to consider the impact of load capacitance, the relation between the sensitivity of step delay and the dominant threshold voltage variation is analytically derived. For complex gates, the multiple process variations for both parallel and stacking structures are equivalently expressed by threshold voltage variation from each transistor. The proposed model has been validated under advanced TSMC (Taiwan Semiconductor Manufacturing Company) 12 nm technology at subthreshold region and achieves excellent agreement with Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation results with the max error less than 6.49% for standard deviation of gate delay and 4.63%/6.40% for max/min delay, demonstrating over 4 times precision improvement compared with competitive analytical models.

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Section: Resultsmentioning

confidence: 99%

Section: Timing Variation Model For Input Slew In Transitional Regionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Cao

et al. 2023

Electronics

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“…Local variation effects have posed huge challenges to timing estimation. To solve this problem, a semianalytical statistical delay model is proposed, which combines analytical and simulation-based method for the subthreshold region [75] . The innovation points are as follows: (1) When the input is fast or slow, the sources of gate delay variation are divided into process parameter variation of the current stage and input slew variation.…”

Section: Our Workmentioning

confidence: 99%

Near-Threshold Wide-Voltage Design Review

Zhao

Yang

Chen

et al. 2023

Tsinghua Sci. Technol.

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This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower, and the energy efficiency is increased by 3-4 times.

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Design of High Precision Temperature Sensor with Current Gain Compensation Technology for On-Chip Application

Luo

2023

Journal of Nanoelectronics and Optoelectronics

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The integration of on-chip temperature sensors within various systems, industrial Internet of Things (IoT), and wireless sensor networks is greatly facilitated by their small size, cost-effectiveness, and capability to provide direct digital output. However, the diverse application scenarios pose challenges in designing these sensors. On one hand, real-time clock calibration demands high-precision temperature sensors, while on-chip heat management emphasizes compactness and low-voltage operation. Additionally, streamlining the calibration cost for mass production holds significant practical value. Addressing these challenges, this study systematically investigates on-chip complementary metal-oxide-semiconductor (CMOS) temperature sensors based on distinct signal domains processed by temperature readout circuits. Specifically, the research commences by analyzing the issues of several degeneracy points in the front-end circuit of a bipolar junction transistor (BJT) temperature sensor with current gain compensation technology. To address the intricate design challenges in advanced technologies and calibration complexities in industrial applications, dynamic component matching, current gain compensation, and chopper stabilization are harnessed. A novel dynamic current gain canceling technique for temperature readout is introduced, enhancing temperature measurement accuracy without incurring additional power consumption or area overhead. Ultimately, an all-digital CMOS temperature sensor is realized using the SMIC 55 nm CMOS process. Occupying a mere 0.29 mm2 of core area, the design operates efficiently across a wide supply voltage range of 1.2 V to 3.6 V. Covering a temperature spectrum from −40 °C to 125 °C, the sensor demonstrates a calibration error of just ±0.7 °C. This achievement is attributed to the incorporation of the proposed dynamic current gain compensation technique.

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Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits

Cited by 3 publications

References 25 publications

Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Near-Threshold Wide-Voltage Design Review

Design of High Precision Temperature Sensor with Current Gain Compensation Technology for On-Chip Application

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