Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Abstract

Subthreshold design provides the promising advantage of low power consumption at the cost of performance variation and even circuit failure. An accurate and efficient statistical timing model is crucial for timing analysis and performance optimization guidance. Prior works lack the consideration of the impact of slew time or the transitional region for input slew due to process variation and efficient approaches considering the impact of load capacitance and multiple process variations in complex gates, resulting in accuracy loss. In this work, an accurate end efficient gate delay variation model is analytically derived for various input slews and load capacitances. The transitional region between fast and slow input slew is efficiently partitioned with an adaptive error tolerance method so as to characterize timing variation by linear interpolation based on that for fast and slow input slew. In order to consider the impact of load capacitance, the relation between the sensitivity of step delay and the dominant threshold voltage variation is analytically derived. For complex gates, the multiple process variations for both parallel and stacking structures are equivalently expressed by threshold voltage variation from each transistor. The proposed model has been validated under advanced TSMC (Taiwan Semiconductor Manufacturing Company) 12 nm technology at subthreshold region and achieves excellent agreement with Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation results with the max error less than 6.49% for standard deviation of gate delay and 4.63%/6.40% for max/min delay, demonstrating over 4 times precision improvement compared with competitive analytical models.