Self-timed pipeline with adder

Compton, Jim; Albicki, A.

doi:10.1109/glsv.1992.218357

Cited by 3 publications

(4 citation statements)

References 2 publications

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“…It is designed with single-rail transmission gale logic, except for the carry output. Dual rail carry outputs (Ci and Ci-) are generated from single rail inpuis and are precharged to low in the absence of a trigger input [3], which is the completion signal from the previous bit RDYi-1 (Fig. lb).…”

Section: Addermentioning

confidence: 99%

“…Multiple valued logic is constrained by heavy hardware overheads. Transition detection schemes based on delay blocks exist [3,4]. Delay blocks also depend on the simulated worst case delay of a component in order to generate a completion signal indicating the end of computation.…”

Section: Introductionmentioning

confidence: 99%

“…[3]. This delayed signal ADDREQ is delayed further by each handshake block and is presented at the output when all the bits have valid outputs.…”

mentioning

confidence: 99%

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Self-timed adder with pipelined output

Dhanesha

Albicki

Proceedings of 36th Midwest Symposium on Circuits and Systems

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This paper presents the design of a self-timed adder, with event driven logic and pipelined output. The scheme makes the individual outputs of bit-wise additions independent of the preceding bits, resulting in high throughput at the cost of initial latency and hardware overheads. Simulation results based on parameters extracted from VLSI implementation of a model 4-bit adder are used to illustrate the performance. The design was implemented with transmission gates in 2-micron CMOS technology. Expansibility to larger adders is shown to give the same performance benefits.

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Section: Addermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Self-timed adder with pipelined output

Dhanesha

Albicki

Proceedings of 36th Midwest Symposium on Circuits and Systems

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“…An asynchronous pipelined ripple-carry adder is presented in [33], along with a circuit that detects the completion o f the addition operation. The results seem to be promising, although the micropipeline implementation presented in [30] is much simpler and there is no real purpose to implementing a complicated detection circuit.…”

Section: Literature Study Of Asynchronous Circuitsmentioning

confidence: 99%

Multi-threshold asynchronous pipeline circuits

Shreih¹

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Direction du Patrimoine de I'edition 395, rue W ellington Ottawa ON K1A 0N4 Canada i * i Canada R eproduced with perm ission o f the copyright owner. F urther reproduction prohibited w itho ut perm ission. AbstractPower consumption o f integrated circuits has been rapidly increasing over the past decades, and this is expected to continue for the foreseeable future due to increasing integration and higher frequencies o f operation. High power consumption results in shorter battery life and excessive heat generation, which negatively affects reliability and necessitates the design o f complex cooling systems. Therefore, it is essential to develop techniques for low power design while maintaining high performance.This thesis is focused on using multi-threshold circuit-level techniques that maintain high performance while allowing a reduction in the power supply voltage in order to reduce power consumption. These techniques are applied to asynchronous circuits, including micropipelines and GasP pipelines. The resulting circuits are then simulated and compared. This is the first attempt, as far as we know, that combines multi-threshold and asynchronous circuit techniques. As such, multi-threshold C-Element and GasP circuit structures are proposed to take advantage of multi-threshold voltage techniques to minimize static power dissipation and to maximize performance. Applications o f multi threshold voltage techniques to delay elements and dual edge-triggered flip flops, both o f which are used in asynchronous micropipelines, are also examined. Also, two application circuits are designed including custom layout. The selected application circuits are a micropipeline FIFO and a pipelined GasP 16-bit Brent Kung adder. Post-Layout extracted simulations are then run on these application circuits to prove the concept.ii R eproduced with perm ission o f the copyright owner. F urther reproduction prohibited w itho ut perm ission.The proposed multi-threshold C-Element based pipelines were found to outperform standard micropipelines by achieving higher performance and lower dynamic and static power dissipation. These include new C-Element structures that were designed specifically to take advantage o f multi-threshold techniques. The proposed multi threshold GasP pipeline outperformed standard GasP pipelines as well. It also performed better than the proposed multi-threshold C-Element based pipelines.

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A self-timed method to minimize spurious transitions in low power CMOS circuits

Balsara

Lee

Proceedings of 1994 IEEE Symposium on Low Power Electronics

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Self-timed pipeline with adder

Cited by 3 publications

References 2 publications

Self-timed adder with pipelined output

Self-timed adder with pipelined output

Multi-threshold asynchronous pipeline circuits

A self-timed method to minimize spurious transitions in low power CMOS circuits

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