Self-Immunity Technique to Improve Register File Integrity Against Soft Errors

Amrouch, Hussam; Henkel, Joerg

doi:10.1109/vlsid.2011.68

Cited by 19 publications

(11 citation statements)

References 15 publications

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“…As can be seen in Figure 6, the trapping-detrapping model (Equation 4) results in a 45% lower shift in V th than the reaction-diffusion model after one year.…”

Section: B Negative Bias Temperature Instabilitymentioning

confidence: 87%

“…Unlike faults induced by soft errors, where systems may correct them during runtime at a low cost [4], permanent faults are more dangerous as they cannot be easily treated and capable to negatively affect chip lifetime [7]. Additionally, excrescent temperatures are also responsible for generating timing errors as an increase of 10 • C may increase interconnect delay by around 5% [16].…”

Section: Introductionmentioning

confidence: 99%

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Thermal management for dependable on-chip systems

Henkel

Ebi

Amrouch

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…As can be seen in Figure 6, the trapping-detrapping model (Equation 4) results in a 45% lower shift in V th than the reaction-diffusion model after one year.…”

Section: B Negative Bias Temperature Instabilitymentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

Thermal management for dependable on-chip systems

Henkel

Ebi

Amrouch

et al. 2013

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…For embedded (in-order) cores, some prior work focuses on pure hardware solutions [Blom et al 2006;Fazeli et al 2010;Amrouch and Henkel 2011;Hu et al 2009b]. Blom et al [2006] and Fazeli et al [2010] proposed register caching mechanisms to only protect the cached registers either by SEU-tolerant latches [Fazeli et al 2010] or Cyclic Redundancy Check (CRC) [Blom et al 2006].…”

Section: Hw-onlymentioning

confidence: 99%

“…Blom et al [2006] and Fazeli et al [2010] proposed register caching mechanisms to only protect the cached registers either by SEU-tolerant latches [Fazeli et al 2010] or Cyclic Redundancy Check (CRC) [Blom et al 2006]. Other approaches protect narrow bits values either by storing ECC codes [Amrouch and Henkel 2011] or duplicating the content of lower-half word to higher-half [Hu et al 2009b]. These approaches are restricted to limited data range and are constrained by high power overhead of ECC checking logic.…”

Section: Hw-onlymentioning

confidence: 99%

A Joint SW/HW Approach for Reducing Register File Vulnerability

Tabkhi

Schirner

2015

ACM Trans. Archit. Code Optim.

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The Register File (RF) is a particularly vulnerable component within processor core and at the same time a hotspot with high power density. To reduce RF vulnerability, conventional HW-only approaches such as Error Correction Codes (ECCs) or modular redundancies are not suitable due to their significant power overhead. Conversely, SW-only approaches either have limited improvement on RF reliability or require considerable performance overhead. As a result, new approaches are needed that reduce RF vulnerability with minimal power and performance overhead.This article introduces Application-guided Reliability-enhanced Register file Architecture (ARRA), a novel approach to reduce RF vulnerability of embedded processors. Taking advantage of uneven register utilization, ARRA mirrors, guided by a SW instrumentation, frequently used active registers into passive registers. ARRA is particularly suitable for control applications, as they have a high reliability demand with fairly low (uneven) RF utilization. ARRA is a cross-layer joint HW/SW approach based on an ARRA-extended RF microarchitecture, an ISA extension, as well as static binary analysis and instrumentation. We evaluate ARRA benefits using an ARRA-enhanced Blackfin processor executing a set of DSPBench and MiBench benchmarks. We quantify the benefits using RF Vulnerability Factor (RFVF) and Mean Work To Failure (MWTF). ARRA significantly reduces RFVF from 35% to 6.9% in cost of 0.5% performance lost for control applications. With ARRA's register mirroring, it can also correct Multiple Bit Upsets (MBUs) errors, achieving an 8x increase in MWTF. Compared to a partially ECC-protected RF approach, ARRA demonstrates higher efficiency by achieving comparable vulnerability reduction at much lower power consumption. ACM Reference Format:Hamed Tabkhi and Gunar Schirner. 2015. A joint SW/HW approach for reducing register file vulnerability.

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“…The reason is that most data in registers cannot cover all 32 bits [18]. Therefore, the highest order bit is most sensitive to NBTI effect.…”

Section: Qb (Mv) Q (Mv)mentioning

confidence: 99%