Self-heating on bulk FinFET from 14nm down to 7nm node

Jang, Doyoung; Bury, E.; Ritzenthaler, R.; Bardon, M. Garcia; Chiarella, T.; Miyaguchi, K.; Raghavan, Praveen; Mocuta, A.; Groeseneken, G.; Mercha, A.; Verkest, D.; Thean, A.

doi:10.1109/iedm.2015.7409678

Cited by 48 publications

(28 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition to being multiple-time programmable (MTP), CTT based memory offers a better alternative to existing onetime programmable (OTP) technologies like eFUSE [2] and gate breakdown anti-fuse [3] as it can be used more effectively for yield improvement, field configurability, performance tailoring, and security enhancements such as chip IDs and onchip reconfigurable encryption key and firmware storage with lower power, higher density, and higher scalability, at no additional processing cost. This intrinsic self-heating enhanced charge trapping memory solution is applicable to SOI as well as bulk FinFET technologies as self-heating in bulk FinFETs, while generally less than SOI FinFETs, is comparable to SOI planar devices and increases considerably with scaling [4], [5].…”

mentioning

confidence: 95%

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Khan

Cartier

Woo

et al. 2017

IEEE Electron Device Lett.

View full text Add to dashboard Cite

The availability of on-chip non-volatile memory for advanced high-k-metal-gate CMOS technology nodes has been limited due to integration and scaling challenges as well as operational voltage incompatibilities, while its need continues to grow rapidly in modern high-performance systems. By exploiting intrinsic device self-heating enhanced charge trapping in as fabricated highk-metal-gate logic devices, we introduce a unique multipletime programmable embedded non-volatile memory element, called the 'charge trap transistor' (CTT), for high-kmetal-gate CMOS technologies. Functionality and feasibility of using CTT memory devices have been demonstrated on 22 nm planar and 14 nm FinFET technology platforms, including fully functional product prototype memory arrays. These transistor memory devices offer high density (∼0.144µm 2 /bit for 22 nm and ∼0.082µm 2 /bit for 14 nm technology), logic voltage compatible and low peak power operation (∼4mW), and excellent retention for a fully integrated and scalable embedded non-volatile memory without added process complexity or masks. Index Terms-High-k-metal-gate, CMOS, embedded non-volatile memory. I. INTRODUCTION T HERE is an ever-increasing need for on-chip memory in VLSI technologies. In this letter, we demonstrate the application of HfO 2 based high-k-metal-gate (HKMG) logic devices, called 'Charge Trap Transistors' (CTTs), as nonvolatile memory (NVM) elements for system-on-chip (SoC) applications in state-of-the-art CMOS technologies. Recently, we demonstrated that intrinsic self-heating enhanced charge trapping in HKMG devices can be used to achieve large and stable device threshold voltage (V T) shifts that are suitable Manuscript

show abstract

mentioning

confidence: 95%

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Khan

Cartier

Woo

et al. 2017

IEEE Electron Device Lett.

View full text Add to dashboard Cite

show abstract

“…Therefore, recent HCD studies of FinFET devices predict lifetime through simple compact modeling based on measurements [9], [10]. In addition, as the channel thickness decreases, the self-heating effect becomes more severe and the influence of temperature on HCD increases [11]. However, few studies analyze HCD through fundamental physical mechanisms, and many researches are focused on empirical modeling based on measurement.…”

Section: Introductionmentioning

confidence: 99%

Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation

Kim

Hong

Shin

2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…3D device structures such as Fin-FETs, nanowires [7][8][9][10][11][12] are used to strengthen the electrostatic control and improve the subthreshold properties. However, serious self-heating effects (SHE) are predictable [13][14][15][16][17][18] due to new materials and non-planar structures. For Germanium, bulk thermal conductivity is 53 W/m/K [19], lower than Silicon (148 W/m/K) [19], which means a weaker ability to dissipate heat out of hotspots.…”

Section: Introductionmentioning

confidence: 99%

“…A more serious SHE can be expected in Ge FinFETs than in Si FinFETs. Although some experimental studies have shown serious SHEs in Ge FinFETs [15,20], the systematical investigation of geometry impact on self-heating in Ge FinFETs is not yet reported. In this work, 3D electro-thermal device simulations are performed to investigate the SHE in the 14 nm Ge p-channel FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

Yin

Shen

Jiang

et al. 2017

Sci. China Inf. Sci.

View full text Add to dashboard Cite

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourierś law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 µm 2 K/W and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

show abstract

Self-heating on bulk FinFET from 14nm down to 7nm node

Cited by 48 publications

References 4 publications

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- $k$ -Metal-Gate CMOS Technologies

Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

Contact Info

Product

Resources

About