Self-heating enhanced charge trapping effect for InGaZnO thin film transistor

Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

“…In previous literatures, threshold voltage shift results from electrons trapping at the IGZO/SiO 2 interface or in SiO 2 bulk under positive gate bias stress (PGBS), [50][51][52][53] or high current stress. 54,55 However, in our research, we found that threshold voltage increases at a shorter channel length for devices with large channel width and operated at high drain voltage (Figures 1 and 2) without imposing stress biases, unlike that found in previous literature.…”

“…When the large channel width and/or short channel length TFT is operated at high drain voltage, significant selfheating effect will occur, and channel electrons will be trapped at the IGZO/SiO 2 interface or in SiO 2 bulk through the thermionic-field emission process, resulting in a larger observed threshold voltage. [54][55][56] In addition, from Figure 1(a), note that threshold voltage shifts with a small variation of the slope in the transfer characteristics. This indicates that some shallow sub-conduction band trap states are created at the IGZO active layer/gate dielectric interface during the self-heating-induced trapping process, resulting in a small amount mobility and subthreshold swing degradation.…”

“…Furthermore, from previous literature, cooling time is also an important factor influencing the Joule heating to occur within the channel. 55 As a result, if on-state current degradation does indeed result from the self-heating effect-induced charge trapping phenomenon, the deterioration degree should decrease as the cooling time, i.e., the base time, increases. As shown in Figure 8(b), when the base time is 10 ms, the deterioration approaches that of conventional I D -V D measurement, and decreases when the base time increases.…”

Analysis of Instability Mechanism under Simultaneous Positive Gate and Drain Bias Stress in Self-Aligned Top-Gate Amorphous Indium-Zinc-Oxide Thin-Film Transistors

“…Thus, the increase in trapped hole by the increase of W ch can be explained with the increase in probability of trapping generated by W ch , not the hole concentration. This also can be well explained through thermally enhanced hole trapping into buffer layer due to the self-heating [6,16]. Since thermal emission enhances the hole trapping by Poole-Frenkel effect in simulation [17], wider W ch corresponds with concentration of hole trapping in the buffer layer under SPGDBS simulation shown in Fig.…”

“…4(b) and (c), respectively. The electron-hole pair can be generated by impact ionization at drain edge [6,16] because SPGDBS is high current stress as shown in Fig. 4(b).…”