Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric

Reliability of silicon integrated circuits

“…To compensate, analogs of the techniques used to improve Al The data indicate that current density exponent can vary between 1 and 2 depending on the relative importance of void nucleation and growth to the failure time. electromigration performance have been introduced for Cu: namely, Cu alloys to limit fast grain boundary diffusion [79][80][81][82][83][84], which controls the rate of electromigration in highly scaled Cu, and the incorporation of metallic cap layers at the Cu surface to impede diffusion along the top surface of the Cu [85,86].…”

Carbon Nanotubes and Graphene Nanoribbons: Potentials for Nanoscale Electrical Interconnects

“…As compared to Cu/low-k interconnects, CNTs offer numerous advantages, as a results of the very strong nature of the C-C bonds, their 1D tubular shape and the electronic band structure. To benchmark Cu-based interconnects, carbon nanotubes have specific properties and fulfill the following requirements: (i) reduced resistance, in fact in the limit of short interconnects there exists a limitation associated to the quantum resistance of a single tube (for metallic SWNTs, the quantum of resistance is 6.5 kΩ [18], while for long interconnects the conductivity of nanotubes in densely-packed bundles is predicted to outperform copper counterpart; (ii) resistance to electromigration, due to the strong carbon-to-carbon bonds within the hexagonal lattice of the shell(s), resulting in the possibility by the tube to sustain elevated current density (10 9 A/cm 2 ), while for copper equivalent current density of 10 6 A/cm 2 already is capable of producing structural damages; (iii) large thermal conductivity, in fact isolated carbon nanotubes are predicted to have large values of thermal conductivity (few thousands W/mK [19,20]).…”

Diffusion Barriers

“…The implementation of a Cu(2 at% Mn) seed layer into the dual damascene process results in the formation of an about 2 nm thick continuous MnSi x O y diffusion barrier at the Cu/SiO 2 interfaces of the via sidewalls and the interconnect trenches. Implementing this barrier technology in combination with a porous SiO x C y (k = 2.3)/porous polyarylene ether (k = 2.3) hybrid dielectric, more than 90 % yield for wiring and via-chain and 70 % reduction in via resistance compared to the conventional Ta-based process were reported [240]. The growth of the MnSi x O y barrier follows a logarithmic rate law at T = 350 °C and 450 °C, which represents a field-enhanced growth mechanism in the early stage and self-limiting growth behavior in the late stage.…”