Self-Controlled High-Performance Precharge-Free Content-Addressable Memory

Mahendra, Telajala Venkata; Mishra, Sandeep; Dandapat, Anup

doi:10.1109/tvlsi.2017.2685427

Cited by 32 publications

(5 citation statements)

References 13 publications

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“…PF-CAM also avoids charge sharing of NAND-CAM cells, but it suffers from degraded performance due to a series chain of MLs. To improve the performance of PF-CAM design further, in [10] SCPF-CAM ML was designed, in which output control is based on the charge at each CAM cell node. This design is developed to improve the performance but at the cost of power consumption.…”

Section: Content Addressable Memorymentioning

confidence: 99%

Dual bit control low-power dynamic content addressable memory design for IoT applications

Satyanarayana¹,

Sridevi²

2021

Turk J Elec Eng & Comp Sci

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The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speed applications. Many search engines of IoT applications require low power consumption and high-speed content addressable memory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardware device used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper, a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. The proposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match line output for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design to perform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented using a CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. The simulation results show that the proposed design reduces power and search delay when compared to conventional DCAM designs.

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Section: Content Addressable Memorymentioning

confidence: 99%

Dual bit control low-power dynamic content addressable memory design for IoT applications

Satyanarayana¹,

Sridevi²

2021

Turk J Elec Eng & Comp Sci

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“…The pre charging of ML will create a problem of increasing the power consumption, in order to reduce the power consumption, pre charge can be avoided in Pre Charge Free Content Addressable Memory so the number of SC path is getting reduced and the overall power is also reduced. But the CAM cells are cascaded in PFCAM so the dependency decreases the speed of operation [12].To increase the speed of operation SCPF CAM is designed, this design is mainly for longer word length at higher frequency of operation with high performance. The control Bit in PFCAM is eliminated so that each CAM cell in this design directly give the output i.e match or miss which don't want to depends on the previous output.…”

Section: Self Controlled Pre Charge Free Cam Architecturementioning

confidence: 99%

Low power CMOS based Self Controlled Precharge Free Content Addressable Memory with Minimum area for Image Processing Devices

Arulpriya¹,

Kumar²

2020

International Journal of Systems Applications, Engineering &Amp; Development

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Image processing devices plays a vital role in several applications like medical, security, biometric etc. The devices ranges from portable size to larger machines with and without Human Computer Interface possibilities. As the image processing and human computer interface system application requires higher memory requirements, the power and area should be small. Searching of data is a high priority work in image classification. To perform high speed search through hardware Content Addressable Memory is used. But the circuit suffers from higher power consumption, precharging issues and low performance. For longer word length the elimination of precharge is needed. So for high speed applications self-controlled precharge-free CAM (SCPF-CAM) is suitable. A 4T hybrid self controlled pre charge free Content Addressable Memory is proposed in this paper using CMOS 32nm technology. The observation shows that the circuit works at high speed, minimizes the search time and has high performance operation. When compared to the conventional SCPF-CAM, 8T CAM the proposed design reduces the number of transistors. The reduction in area is about approximately 20% and can be used in low power and low energy applications. In Synopsis HSPICE Predictive technology models were used for the implementation in 32nm CMOS technology. The work will be extended in future using FinFET technology where the leakage current can be minimized.

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“…Approaches to reduce the power consumption in CAMs have targeted primarily two main components: matchline power and searchline power [1,2,[21][22][23][24][25][26][27][28][29][30][31][32]. In most applications, a much larger number of mismatches occur than matches [32], and hence many techniques have been tailored to reduce the mismatch power consumption.…”

Section: Related Workmentioning

confidence: 99%

“…This technique can be combined with a pipelined search scheme [22] which activates fewer portions of the CAM initially, and then proceeds by activating only those portions which match. To address the precharging power consumption, a pre-charge free design was proposed [23]. A design, which reduces the leakage power in CAM's proposed two novel TCAM cells [24].…”

Section: Related Workmentioning

confidence: 99%

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

Joshi

Ogrenci-Memik

et al. 2018

JLPEA

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Abstract:In this paper, we characterize the interplay between power consumption and performance of a matchline-based Content Addressable Memory and then propose the use of a multi-V dd design to save power and increase post-fabrication tunability. Exploration of the power consumption behavior of a CAM chip shows the drastically different behavior among the components and suggests the use of different and independent power supplies. The complete design, simulation and testing of a multi-V dd CAM chip along with an exploration of the multi-V dd design space are presented. Our analysis has been applied to simulated models on two different technology nodes (130 nm and 45 nm), followed by experiments on a 246-kb test chip fabricated in 130 nm Global Foundries Low Power CMOS technology. The proposed design, operating at an optimal operating point in a triple-V dd configuration, increases the power-delay operation range by 2.4 times and consumes 25.3% less dynamic power when compared to a conventional single-V dd design operating over the same voltage range with equivalent noise margin. Our multi-V dd design also helps save 51.3% standby power. Measurement results from the test chip combined with the simulation analysis at the two nodes validate our thesis.

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Self-Controlled High-Performance Precharge-Free Content-Addressable Memory

Cited by 32 publications

References 13 publications

Dual bit control low-power dynamic content addressable memory design for IoT applications

Dual bit control low-power dynamic content addressable memory design for IoT applications

Low power CMOS based Self Controlled Precharge Free Content Addressable Memory with Minimum area for Image Processing Devices

Multi-Vdd Design for Content Addressable Memories (CAM): A Power-Delay Optimization Analysis

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