Dual bit control low-power dynamic content addressable memory design for IoT applications

Abstract

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speed applications. Many search engines of IoT applications require low power consumption and high-speed content addressable memory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardware device used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper, a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. The proposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match line output for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design to perform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented using a CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. The simulation results show that the proposed design reduces power and search delay when compared to conventional DCAM designs.