Generating quadrature phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common. For example, [1] uses LC-VCOs followed by 2:1 dividers to generate the half-rate clocks for both TX and RX in a 28Gb/s transceiver. However, such an approach tends to be power-and area-inefficient for multi-lane implementations at data rates of 25Gb/s and beyond.We present a quadrature generation method that uses two 30×30μm 2 0.85nH inductors and consumes 3.1mW at 13.5GHz, excluding buffering, while generating quadrature phases at the same frequency with an accuracy of 1.5°. The method generates quadrature signals by adding 20% to the power consumed by a differential LC-VCO. This method is implemented in 28nm CMOS in a receiver designed for 28G very-short-reach and short-reach applications [2]. The receiver exhibits a BER <10 -12 for a 2 7 -1 PRBS pattern through a 7-inch backplane possessing a loss of 6dB at 12GHz. In addition, it also offers the de-skew capability that injection-locked receivers [3] and analog phase interpolators are capable of providing.The quadrature generator uses parametric pumping of a capacitor to produce a phase-shifted version of the driver signal. Similar to injection-locked dividers, it allows us to break the trade-off between quadrature accuracy and phase noise inherent in coupled quadrature LC VCOs. Unlike such dividers, it does so at the same frequency. In this case, the injection is into a resonator, not an independent oscillator, so frequency lock is always guaranteed.The single-ended version of the method is shown in Fig. 23.7.1. Similar to [4], a three-terminal MOS capacitor is used for parametric energy transfer. The resonator consists of a low-Q inductor, a thick-oxide accumulation-mode varactor and a pumped thick-oxide NMOS capacitor. The driver switches the drain-source voltage of the NMOS capacitor between 0V and 1V, changing its capacitance rapidly from inversion to depletion and vice-versa. To conserve the charge stored at the gate, the gate voltage rises for a negative capacitance change or falls for a positive capacitance change, and energy transfer takes place. The efficiency of such a parametric energy transfer mechanism depends on the relative capacitance change (ΔC/C) and the absolute value of the gate voltage (V gate ), and is maximized at the signal peaks when the current through the capacitor is zero [4]. As the tank's resonant frequency approaches the driver's frequency, the peaks of the tank signal get aligned to the zero crossings of the driver, leading to optimal pumping and creating a quadrature relationship between the driver and the tank signals. Such a phase selectivity enables a straightforward way of providing a one-quarter period delay with the use of a single driver stage, thus mitigating the need to use multiple delay stages. The phase noise of t...