Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment

Buchty, Rainer; Mattes, Oliver; Karl, Wolfgang

doi:10.1007/978-3-540-78153-0_9

Cited by 7 publications

(7 citation statements)

References 7 publications

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“…Intelligence had been integrated into the memory itself, so that it is able to process data without the host processor and therefore results in a higher performance (see [7,8]). Especially, FlexRAM and SelfAware Memory (SAM) were developed for this purpose and the decentral management of large memory.…”

Section: Related Workmentioning

confidence: 99%

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Göhringer

Meder

Werner

et al. 2012

International Journal of Reconfigurable Computing

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This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC). The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.

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Section: Related Workmentioning

confidence: 99%

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Göhringer

Meder

Werner

et al. 2012

International Journal of Reconfigurable Computing

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“…Self-aware Memory (SaM) [BMK08] represents a memory architecture, enabling selfmanagement of system components for building up a loosely coupled decentral system architecture without central management instance. Traditionally, memory management tasks are handled software-based such as operating system and program libraries assisted by dedicated hardware components, e.g., the memory management unit or a cache controller.…”

Section: Background and Related Workmentioning

confidence: 99%

“…Prospectively, decentralized systems containing multiple self-managing memory components will arise and be conceivable, possibly in combination with concepts like 3D-stacking of memory [Loh08]. As an example for such a system, Self-aware Memory (SaM) is given [BMK08]. With SaM, memory accesses are processed by self-managing system components.…”

Section: Introductionmentioning

confidence: 99%

Efficient Synchronization Techniques in a Decentralized Memory Management System Enabling Shared Memory

Mattes¹,

Schindewolf²,

Sedler³

et al. 2011

PARS-Mitteilungen

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Abstract:The rising integration level enables combining more logic on a single chip. This is exploited in multiprocessor systems-on-chip (MPSoCs) or manycore research prototypes such as the Intel SCC. These platforms offer access to shared memory over a limited number of controllers which may lead to congestion. In order to scale the memory with the core count, the memory management must become more flexible and distributed in nature. In the near future decentralized systems with multiple selfmanaging memory components will arise.The problem tackled in this paper is how to realize synchronization mechanisms for coincident access to shared memory in such a decentralized memory management system. Furthermore, improvements of the distributed synchronization mechanism are integrated and evaluated. To speed up the synchronization, additional logic in the form of a locks queue, is added. In order to reduce the network traffic this is combined by extending the synchronization protocol with exponential backoff. In the evaluation, side effects of combining both techniques are discussed and explained.

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“…We will outline the used mechanisms and demonstrate how these are generally applicable with respect to parallel, distributed, heterogeneous, and reconfigurable systems. These mechanisms are key to our Selfaware Memory (SaM) [6] architecture, providing flexible assignment and management of memory resources as a way to leverage memory and communication aspects in parallel, heterogeneous, and potentially dynamically changing systems.…”

Section: Introductionmentioning

confidence: 99%

Design Aspects of Self-Organizing Heterogeneous Multi-Core Architectures Entwurfsaspekte selbstorganisierender, heterogener Multicore-Architekturen

Buchty¹,

Karl²

2008

It - Information Technology

Self Cite

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Already today we face architectures featuring up to several hundreds of processors, being able to manage several thousand concurrent threads. Future architectures, however, will not only see an increase in parallelism but also feature an increase in heterogeneity and reconfigurability. Judging from current production and prototype architectures, we also see that such systems will be tiled, i. e., individual cores with local memory interconnected through some means of on-chip communication. Current discussions show that existing approaches to application mapping, parallelization, data locality optimization, and system management do not match these upcoming architectures well, thus rather hampering than harnessing the power of future systems. We will therefore outline the requirements of upcoming architectures and demonstrate how self-organization, including bio-inspired, techniques may help to manage system complexity. Key to these techniques is a sophisticated decentralized, hierarchical monitoring approach suitable for sustained real-time monitoring and event correlation for current and future high-performance architectures.

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Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment

Cited by 7 publications

References 7 publications

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Efficient Synchronization Techniques in a Decentralized Memory Management System Enabling Shared Memory

Design Aspects of Self-Organizing Heterogeneous Multi-Core Architectures Entwurfsaspekte selbstorganisierender, heterogener Multicore-Architekturen

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