Self-aligned metal capping layers for copper interconnects using electroless plating

Gambino, Jeff; Wynne, J.; Gill, Jason M.R.; Mongeon, S.; Meatyard, D.; Lee, B.; Bamnolker, H.; Hall, L.; Li, N.; Hernández, Marianella; Little, Penelope; Hamed, Mohammed S. G.; Иванов, Игорь Анатольевич; Gan, Chee Lip

doi:10.1016/j.mee.2006.09.008

Cited by 67 publications

(57 citation statements)

References 15 publications

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“…500 To reduce some of the complexity of such pitch division / multiple pass patterning schemes, new ES / HM materials and deposition processes are being sought that either provide high or contrasting etch selectivities relative to other materials, 501 or can be selectively deposited / grown on pre-existing patterned structures. [502][503][504] The latter is beyond the scope of this article. However for the former, we biefly review below some of the ES/HM challenges associated with multiple patterning schemes and one material system that could be useful in this regard.…”

Section: 15mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

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Section: 15mentioning

confidence: 99%

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

King

2014

ECS J. Solid State Sci. Technol.

131

115

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“…In this case, the EM lifetime degraded by half for each new generation due to the geometrical scaling of the critical void size 5 . The continuous degradation of EM reliability has stimulated extensive studies in strengthening the cap interface by various methods, including the use of a metal cap (CoWP, CoSnP, Ta) [7][8][9] or a surface alloy (Al) layer 9 before the SiNx cap deposition. Two orders of magnitude of improvement in EM lifetime have been demonstrated by using the CoWP cap [7][8][9] .…”

Section: Introductionmentioning

confidence: 99%

“…The continuous degradation of EM reliability has stimulated extensive studies in strengthening the cap interface by various methods, including the use of a metal cap (CoWP, CoSnP, Ta) [7][8][9] or a surface alloy (Al) layer 9 before the SiNx cap deposition. Two orders of magnitude of improvement in EM lifetime have been demonstrated by using the CoWP cap [7][8][9] . However, a recent study showed that the Cu grain structures were no longer bamboo-like when the Cu line width scaled down to 90 nm 10 .…”

Section: Introductionmentioning

confidence: 99%

Grain Size And Cap Layer Effects On Electromigration Reliability Of Cu Interconnects: Experiments And Simulation

Li-juan

Kraatz

Aubel

et al. 2010

AIP Conference Proceedings

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Articles you may be interested inGrain structure analysis and effect on electromigration reliability in nanoscale Cu interconnects Appl. Phys. Lett. 102, 131907 (2013) Abstract. This paper combined experiments and simulation to investigate the grain size and cap layer effects on electromigration (EM) reliability of Cu interconnects. First the statistical distribution of EM lifetime and failure modes were examined for in laid Cu interconnects of large and small grain structures with two different cap layers of SiCN vs. CoWP. The CoWP cap was found to significantly improve the EM lifetime due to the suppression of the interfacial mass transport as a result of strengthening of the Cu/cap interface bonding. In addition, the grain size was observed to affect the EM reliability significantly, particularly for the CoWP capped structures. Resistance traces and failure analysis revealed two distinct failure modes: mode I with voids formed near the cathode via corner and mode II with voids formed in the trench several microns away from the cathode via. It was found that large grain size and strong cap interface reduced the mass transport rate and the void diffusion in the Cu line, leading to a longer EM lifetime and a higher proportion of mode II failures. A statistical simulation of EM lifetimes was also applied to Cu interconnects with grain structures generated by the Monte Carlo method. The simulation results for different grain sizes and cap interfaces are in good agreement with the experimental observations.

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“…3 Furthermore, a thin Co layer deposited by chemical vapor deposition (CVD) is considered as liner, as it can enhance the uniformity of PVD-Cu, thereby overcoming the seed discontinuity issue in narrow trenches. 2,4 However, for the case of TSV where a further aspect ratio increase is expected in the future, the PVD method will at some point face its intrinsic, physical limitation of an insufficient step coverage. 5 As liner, ruthenium has the advantage of being a platable material and characterization of CMP has previously been reported.…”

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confidence: 99%

“…15,16 In alkaline solution, the Co forms a passivation layer, i.e. Co(OH) 2 , and this passivated Co is less prone to corrosion compared to the situation where the Co liner is exposed to an acidic plating solution. 17 Even an electrodeposition process in alkaline solution still faces challenges when the Co liner thickness is to be scaled further because terminal effects will come into play during the ECD process and this introduces thickness variations across the wafer.…”

mentioning

confidence: 99%

Role of Bath Composition in Electroless Cu Seeding on Co Liner for through-Si Vias

Inoue

Philipsen

Veen

et al. 2014

ECS J. Solid State Sci. Technol.

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To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP).

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Self-aligned metal capping layers for copper interconnects using electroless plating

Cited by 67 publications

References 15 publications

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Grain Size And Cap Layer Effects On Electromigration Reliability Of Cu Interconnects: Experiments And Simulation

Role of Bath Composition in Electroless Cu Seeding on Co Liner for through-Si Vias

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