Selective silicon-on-insulator (SOI) implant: a new micromachining method without footing and residual stress

Park, Sangjun; Kwak, Donghun; Ko, Hyoungho; Song, Taeyong; Cho, Dong‐il Dan

doi:10.1088/0960-1317/15/9/001

Cited by 15 publications

(5 citation statements)

References 13 publications

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“…Although residual stress in SOI wafers can vary enormously, the top silicon layer should present mainly a tensile stress, as shown by several works. 21,22 Furthermore, as reported in ref 21, the residual tensile stress is relatively small in substrates with top layer thicknesses considered in our work. Phenomena that can induce a compressive stress must be considered in order to explain the bending of SiNWs.…”

Section: Resultssupporting

confidence: 82%

Correlation between Surface Stress and Apparent Young’s Modulus of Top-Down Silicon Nanowires

2012

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In this work, we report experimental evidence of surface stress effects on the mechanical properties of silicon nanostructures. As-fabricated, top-down silicon nanowires (SiNWs) are bent up without any applied force. This self-buckling is related to the surface relaxation that reaches an equilibrium with bulk deformation due to the material elasticity. We measure the SiNW self-deformation by atomic force microscopy (AFM), and we apply a simple physical model in order to give an estimation of the surface stress. If the equilibrium is altered by a nanoforce, applied by an AFM tip, nanowires find a new equilibrium condition bending down (mechanical bistability). In this work, for the first time, we report a clear and quantitative relationship between the SiNWs' apparent Young's modulus, measured by force-deflection spectroscopy, and the estimated value of surface stress, obtained by self-buckling measurements taking into account the Young's modulus of bulk silicon. This is an experimental confirmation that the surface stress is fundamental in determining mechanical properties of SiNWs, and that the elastic behavior of nanostructures strongly depends on their surfaces.

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Section: Resultssupporting

confidence: 82%

Correlation between Surface Stress and Apparent Young’s Modulus of Top-Down Silicon Nanowires

2012

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“…However, the KOH etching step is often slow and cannot be controlled accurately when fabricating small structures. In order to solve this fabrication issue, Wang et al proposed a single-sided fabrication on a (111) silicon wafer based on the study of its crystallographic and piezoresistive properties [56,57]. Designed to measure lateral shock, two identical devices are placed in parallel to form a full bridge.…”

Section: Piezoresistive Sensorsmentioning

confidence: 99%

Micromachined high-g accelerometers: a review

Narasimhan¹,

Jianmin

2015

J. Micromech. Microeng.

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“…To achieve a suspension gap larger than the buried oxide using conventional SOI wafers, an additional lithography step is needed for the backside, followed by wet-etch or DRIE processing [5]. Cavity-SOI wafers can also help reduce the 'footing' phenomenon caused by buried oxide layers during DRIE [6]. Cavity-SOI structures have been utilized for producing MEMS devices such as resonators, with the advantage that the dimensions of the silicon mass can be defined by optical lithography as in figure 1 (left) [7].…”

Section: Introductionmentioning

confidence: 99%

“…For MEMS devices with thin diaphragms or long thin beams, uncontrolled compressive residual stresses may cause the features to buckle. In addition, the buried cavities are vulnerable to crack initiation and growth if they have sharp corners under tensile residual stress [6]. In other cases such as micro-mirrors, residual stresses are used in the release process to align the electrodes in order to achieve a larger actuation range [11].…”

Section: Introductionmentioning

confidence: 99%

Residual stresses at cavity corners in silicon-on-insulator bonded wafers

Lin¹,

Elkhatib²,

Mäkinen³

et al. 2013

J. Micromech. Microeng.

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Uncontrolled residual stresses in both integrated circuit and micro-electro-mechanical system applications may affect device performance and reliability, making microscale experimental analysis of the residual stresses an essential part of process and quality control. This work studies the residual stresses generated from different processing parameters common in the manufacture of silicon-on-insulator wafers with buried cavities (cavity-SOI). The buried cavities can concentrate the residual stresses and generate localized mechanical failures. Infrared photoelasticity and optical profilometry are used here to analyze the stress state in wafers after each of several critical processing steps, each with different process parameters. It is found that the residual stresses associated with cavities in the bonded wafers may significantly increase depending upon the oxidation/etching steps and that the stress magnitude is dependent upon the particular etched cavity geometry. Process-dependent stress states and their generation mechanisms are explained for each processing step. The oxide layer grown on cavity sidewalls is found to significantly impact the residual stress at the cavity corners, with a strong dependence on buried oxide layer thickness. By selecting appropriate processing steps and parameters, the magnitude and orientation of the residual stress in the cavity-SOI wafers can be controlled to enhance reliability.

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Selective silicon-on-insulator (SOI) implant: a new micromachining method without footing and residual stress

Cited by 15 publications

References 13 publications

Correlation between Surface Stress and Apparent Young’s Modulus of Top-Down Silicon Nanowires

Correlation between Surface Stress and Apparent Young’s Modulus of Top-Down Silicon Nanowires

Micromachined high-g accelerometers: a review

Residual stresses at cavity corners in silicon-on-insulator bonded wafers

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