Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

Abstract

Abstract:In order to fabricate metal gate/high-k gate stacks utilizing ECR sputtering, selective etching of HfN gate electrodes was investigated. It was found that etching rates of HfN gate electrodes at room temperature were 2.9 and 0.23 nm/s for DHF (1%) and the mixed solution of HF:H 2 O 2 :H 2 O = 1:2:40, respectively. In addition, the etching selectivity for HfN/HfSiON was relatively high, such as the ratio of 65 which was 3 times higher than that of DHF (1%) by the mixed solution. After the in-situ formation of HfN/HfSiON layers on p-Si(100) and post deposition annealing (PDA), pattering of HfN was carried out utilizing the selective etching process. In case the PDA of 800 • C/15 s, the MOS diodes were found to be successfully fabricated, and the equivalent oxide thickness (EOT) of 0.56 nm, and the leakage current at V FB -1 V of 1.3 A/cm 2 were obtained.

In-situ formation of Hf-based MONOS structures for non-volatile memory applications

“…Finally, Al contact layer was ex-situ deposited by evaporation, and gate electrode patterning was carried out for Al/HfN 0.5 to fabricate MONOS diode structures as shown in Fig. 1(a) [16]. For the comparison, Al gate electrode was directly deposited by ex-situ process on the HfO 2 /HfN 1.2 /HfO 2 (ONO) structures as shown in Fig.…”