Selective area growth on planar masked InP substrates by metal organic vapour phase epitaxy (MOVPE)

Caenegem, Tom Van; Moerman, Ingrid; Demeester, Piet

doi:10.1016/s0960-8974(98)00003-5

Cited by 30 publications

(25 citation statements)

References 51 publications

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“…For both growth pressures of 100 and 450 Torr, the nanodots have a much smaller height compared to the thickness of the continuous film in the non-masked area. This observation contradicts to a common expectation for the thickness enhancement in the SAG structures based on a simple gas-phase diffusion model [18]. Even in the case when the lateral size of the mask is smaller than the diffusion length D/k for precursors in the gas phase, the growth enhancement is expected in the SAG region due to formation of an excessive precursor concentration above the masked area.…”

Section: Methodscontrasting

confidence: 69%

Selective growth of GaN nanodots and nanostripes on 6H‐SiC substrates by metal organic vapor phase epitaxy

Goh

Martin

Ould-Saad

et al. 2009

Phys. Status Solidi (c)

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GaN nanodots and nanostripes with smooth sidewall surfaces have been selectively grown on 6H‐SiC substrates by metal organic vapor phase epitaxy. By varying the growth reactor pressure, we have been able to grow either isolated nanostructures or laterally overgrown structures. As confirmed by the Raman scattering and X‐ray diffraction techniques, the nanostructures have no influence of step bunching that occurs in the unmasked area of the continuous GaN film. The frequency shift of the E2 optical phonons shows that the residual strain in the nanostripes is relaxed compared to the continuous GaN film. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Methodscontrasting

confidence: 69%

Selective growth of GaN nanodots and nanostripes on 6H‐SiC substrates by metal organic vapor phase epitaxy

Goh

Martin

Ould-Saad

et al. 2009

Phys. Status Solidi (c)

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“…Current III-V semiconductor device fabrication typically requires the epitaxial growth of III-V compound device materials with various alloy contents on a III-V substrate [7]- [9]. Such epitaxially grown III-V heterostructures can be on the order of nanometers to micrometers in thickness.…”

Section: Difficulties With Conventional Passivation and Planarizamentioning

confidence: 99%

Self-Aligning Planarization and Passivation for Integration Applications in III–V Semiconductor Devices

Demir

Zheng

Sabnis³

et al. 2005

IEEE Trans. Semicond. Manufact.

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Abstract-This paper reports an easy planarization and passivation approach for the integration of III-V semiconductor devices. Vertically etched III-V semiconductor devices typically require sidewall passivation to suppress leakage currents and planarization of the passivation material for metal interconnection and device integration. It is, however, challenging to planarize all devices at once. This technique offers wafer-scale passivation and planarization that is automatically leveled to the device top in the 1-3-m vicinity surrounding each device. In this method, a dielectric hard mask is used to define the device area. An undercut structure is intentionally created below the hard mask, which is retained during the subsequent polymer spinning and anisotropic polymer etch back. The spin-on polymer that fills in the undercut seals the sidewalls for all the devices across the wafer. After the polymer etch back, the dielectric mask is removed leaving the polymer surrounding each device level with its device top to atomic scale flatness. This integration method is robust and is insensitive to spin-on polymer thickness, polymer etch nonuniformity, and device height difference. It prevents the polymer under the hard mask from etchinduced damage and creates a polymer-free device surface for metallization upon removal of the dielectric mask. We applied this integration technique in fabricating an InP-based photonic switch that consists of a mesa photodiode and a quantum-well waveguide modulator using benzocyclobutene (BCB) polymer. We demonstrated functional integrated photonic switches with high process yield of 90%, high breakdown voltage of 25 V, and low ohmic contact resistance of 10 . To the best of our knowledge, such an integration of a surface-normal photodiode and a lumped electroabsorption modulator with the use of BCB is the first to be implemented on a single substrate.

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“…The sloped area near the SAG mask edge corresponds to the (111)B crystal plane. Epitaxy grows slower on this plane than on the (001) plane because the dangling bond density of the (111)B plane is approximately 42% lower than on the (001) plane [19]. During growth, Group III reactants migrate from the lower bonding density (111)B plane to the higher bonding density (001) plane, creating the spiked-shape feature near the mask edge.…”

Section: Selective Area Growth Integrationmentioning

confidence: 99%

“…To avoid these problems, we developed a monolithic integration technique that we discuss in the next section. The technique employs selective area growth (SAG) [19]- [22] based on metal-organic chemicalvapor deposition (MOCVD) [23]. This approach enables approximately planar, side-by-side integration of separate PD and EAM structures, without compromising individual component design.…”

Section: B Pd-eam Switch Circuit-integration Requirementsmentioning

confidence: 99%

“…Since deposition does not occur on the SAG mask, there is a larger proportion of In species near the mask edge than further away. An alternative explanation [19] suggests that it is easier to break a methyl-indium bond compared to a methylgallium bond at the substrate surface, allowing for the increased incorporation of In compared to Ga near the mask edge.…”

Section: Selective Area Growth Integrationmentioning

confidence: 99%

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Intimate monolithic integration of chip-scale photonic circuits

Sabnis

Demir

Fidaner

et al. 2005

IEEE J. Select. Topics Quantum Electron.

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Abstract-In this paper, we introduce a robust monolithic integration technique for fabricating photonic integrated circuits comprising optoelectronic devices (e.g., surface-illuminated photodetectors, waveguide quantum-well modulators, etc.) that are made of completely separate epitaxial structures and possibly reside at different locations across the wafer as necessary. Our technique is based on the combination of multiple crystal growth steps, judicious placement of epitaxial etch-stop layers, a carefully designed etch sequence, and self-planarization and passivation steps to compactly integrate optoelectronic devices. This multigrowth integration technique is broadly applicable to most III-V materials and can be exploited to fabricate sophisticated, highly integrated, multifunctional photonic integrated circuits on a single substrate. As a successful demonstration of this technique, we describe integrated photonic switches that consume only a 300 × 300 µm footprint and incorporate InGaAs photodetector mesas and InGaAsP/InP quantum-well modulator waveguides separated by 50 µm on an InP substrate. These switches perform electrically-reconfigurable optically-controlled wavelength conversion at multi-Gb/s data rates over the entire center telecommunication wavelength band.

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Selective area growth on planar masked InP substrates by metal organic vapour phase epitaxy (MOVPE)

Cited by 30 publications

References 51 publications

Selective growth of GaN nanodots and nanostripes on 6H‐SiC substrates by metal organic vapor phase epitaxy

Selective growth of GaN nanodots and nanostripes on 6H‐SiC substrates by metal organic vapor phase epitaxy

Self-Aligning Planarization and Passivation for Integration Applications in III–V Semiconductor Devices

Intimate monolithic integration of chip-scale photonic circuits

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