SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

Uemura, Tomomasa; Tosaka, Y.; Matsuyama, Hideya; Shono, K.; Uchibori, Chihiro J.; Kondo, Takahisa; Fukuda, Mitsuhiro; Hatanaka, K.

doi:10.1109/irps.2010.5488827

Cited by 43 publications

(12 citation statements)

References 7 publications

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“…As known, layout placement is a key factor which could affect multi-node charge collection. And many approaches, such as soft error immune latch (SEILA) [8], layout design through error aware transistor positioning (LEAP) [9], are presented to harden the sensitive nodes in the layout placement.…”

Section: Layout Placement Designmentioning

confidence: 99%

A novel reliable SEU hardened latch to mitigate multi-node charge collection

Zhang¹,

Zhuangsi²

2012

IET International Conference on Information Science and Control Engineering 2012 (ICISCE 2012)

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Many redundancy based hardened latch would become invalid when multiple nodes collect charge concurrently. To mitigate multi-node charge collection, a novel latch based on the combinational of layout and circuit design is proposed. The number of sensitive node pairs is reduced by the circuit design. And by adjusting the placement the sensitive transistors in the layout, the distance between sensitive transistors is increased. SPICE simulation results illustrate that the proposed latch significantly reduce the number of sensitive node pairs. The performance of mitigating multinode charge collection is improved.

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Section: Layout Placement Designmentioning

confidence: 99%

A novel reliable SEU hardened latch to mitigate multi-node charge collection

Zhang¹,

Zhuangsi²

2012

IET International Conference on Information Science and Control Engineering 2012 (ICISCE 2012)

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“…The research work of Gaspard et al pointed out the hardening performance of the DICE is largely reduced at advanced technologies [9]. Several layout techniques, such as soft error immune latch (SEILA) [10], layout design through error aware transistor positioning (LEAP) [11], have been proposed to attenuate the charge collection on multi-node. And at circuit-level, Katsarou et al proposed the DNCS-SEU tolerant latch to deal with the charge sharing [12].…”

Section: Introductionmentioning

confidence: 99%

Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches

Zeng

2015

IEICE Electron. Express

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In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of the circuit structure and layout placement is adopted to enhance the multiple nodes upset tolerance. This latch consists of a normal D latch and a typical DICE latch. Different from the TMR latch, this latch can mitigate the charge collection on two transistors. HSPICE simulation results present that there only exit four sensitive transistor pairs in this latch. Compared to the typical DICE and DMR latch, the sensitive transistor pairs are largely reduced. And by adjusting the layout placement, these sensitive transistor pairs are separated from each other as much as possible. From the view of the layout, it is almost impossible for charge collection on the sensitive transistor pairs in our proposed latch.

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“…Several layout-level approaches are presented to reduce the multi-node charge collection [12,13]. There layout-level approaches are difficult to be applied to the standard cells as the layout height of the latches is changed.…”

Section: Introductionmentioning

confidence: 99%