Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches

Abstract

In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of the circuit structure and layout placement is adopted to enhance the multiple nodes upset tolerance. This latch consists of a normal D latch and a typical DICE latch. Different from the TMR latch, this latch can mitigate the charge collection on two transistors. HSPICE simulation results present that there only exit four sensitive transistor pairs in this latch. Compared to the typical DICE and DMR latch, the sensitive transistor pairs are largely reduced. And by adjusting the layout placement, these sensitive transistor pairs are separated from each other as much as possible. From the view of the layout, it is almost impossible for charge collection on the sensitive transistor pairs in our proposed latch.

MSIFF: A radiation-hardened flip-flop via interleaving master-slave stage layout topology

“…Technology scaling has increased the vulnerability of flipflops to single-event upset (SEU) [1,2,3]. Reduced nodal capacitance and supply voltage decrease the critical charge required to upset [4,5,6,7]. Close proximity of transistors results in charge sharing at multiple nodes [8,9,10,11,12,13].…”

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

“…Well isolation, guard rings and layout techniques were utilized to solve the multiple upsets caused by charge sharing, but benefits of these techniques are quite limited [9,10]. In order to solve this severe problem, researchers have proposed plenty of latches which can effectively tolerate the DUs [11][12][13][14][15][16][17]. The latch designed in [12] employed a modified triple path dual-interlocked storage cell (TPDICE) [11] and Muller C-element (MCE), acquiring better tolerance.…”

“…The latch designed in [12] employed a modified triple path dual-interlocked storage cell (TPDICE) [11] and Muller C-element (MCE), acquiring better tolerance. As for DNCS (Double-Node Charge Sharing) latch in [13] and CLCT (Circuit and Layout Combination Technique) latch in [14], both latches utilized interlocked structure and MCE to obtain the robustness. However, the latch in [14] was not fully SEDU tolerant in the circuit design level, and further, layout technique was used to harden the latch.…”

“…As for DNCS (Double-Node Charge Sharing) latch in [13] and CLCT (Circuit and Layout Combination Technique) latch in [14], both latches utilized interlocked structure and MCE to obtain the robustness. However, the latch in [14] was not fully SEDU tolerant in the circuit design level, and further, layout technique was used to harden the latch. The Delta DICE in [15], DONUT (Double Node Upset Tolerant) in [16], and DNURL (Double-Node-Upset-Resilient Latch) in [17] were derived by the applications of feedback loop.…”

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

“…Dual-interlocked cell (DICE) is widely used to mitigate the SEU sensitivity of flip-flops [5,6,7]. It was firstly described in [8] and it is immune to SEU caused by charge collection at a single node.…”