Sehwa: a software package for synthesis of pipelines from behavioral specifications

Park, N.; Parker, Alice C.

doi:10.1109/43.3169

Cited by 330 publications

(103 citation statements)

References 8 publications

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“…With very little additional hardware, the throughput of a data can be improved by pipelining the path 1143, [22]. A pipelined data path (also called functional pipelining) is a data path in which operations of different instances can be performed concurrently.…”

Section: Considerations In Data-path Synthesismentioning

confidence: 99%

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A formal approach to the scheduling problem in high level synthesis

Hwang

Lee

Hsu

1991

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

350

111

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Section: Considerations In Data-path Synthesismentioning

confidence: 99%

“…Two consecutive tasks can be initiated with a certain interval, which is called the latency of the pipelined data path. In [22], a theorem for pipelined data path is available, stated as the following.…”

Section: Functional Pipelining (Pipelined Data Path)mentioning

confidence: 99%

A formal approach to the scheduling problem in high level synthesis

Hwang

Lee

Hsu

1991

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

350

111

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“…Most of this work is primarily concerned with functional pipelining. Many synthesis tools target instruction-set architectures [10,4,3,14,15,1,9,2]; our tool, on the other hand, targets the more general class of sequential circuits. Other approaches start with a C program [8,5].…”

Section: Related Workmentioning

confidence: 99%

High-level automatic pipelining for sequential circuits

Marinescu¹,

Rinard²

International Symposium on System Synthesis (IEEE Cat. No.01EX526)

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This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation.We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit.

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“…The notion of closeconnection has been dened in several ways, the most com- The input specications usually have a \V" structure, implying that the specication has a large number of operations near the input and relatively smaller number of operations near the outputs. Given that among several list-scheduling algorithms, backward and forward listscheduling algorithms are popular [10], seeding can be either done at the top or the bottom of the specication. Here, we have c hosen to do the seeding at the top.…”

Section: Concurrent P Artitioner/schedulermentioning

confidence: 99%

PARAS: System-level concurrent partitioning and scheduling

Wong¹,

Jain²

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented. PARAS maximizes the overall performance of the nal design and considers dierent c hip congurations and communication structures. Experiments, conducted with specications ranging in size from few to hundreds of operations, demonstrate the success of this approach.

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Sehwa: a software package for synthesis of pipelines from behavioral specifications

Cited by 330 publications

References 8 publications

A formal approach to the scheduling problem in high level synthesis

A formal approach to the scheduling problem in high level synthesis

High-level automatic pipelining for sequential circuits

PARAS: System-level concurrent partitioning and scheduling

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