High-level automatic pipelining for sequential circuits

Abstract

This paper presents a new approach for automatically pipelining sequential circuits. The approach repeatedly extracts a computation from the critical path, moves it into a new stage, then uses speculation to generate a stream of values that keep the pipeline full. The newly generated circuit retains enough state to recover from incorrect speculations by flushing the incorrect values from the pipeline, restoring the correct state, then restarting the computation.We also implement two extensions to this basic approach: stalling, which minimizes circuit area by eliminating speculation, and forwarding, which increases the throughput of the generated circuit by forwarding correct values to preceding pipeline stages. We have implemented a prototype synthesizer based on this approach. Our experimental results show that, starting with a non-pipelined or insufficiently pipelined specification, this synthesizer can effectively reduce the clock cycle time and improve the throughput of the generated circuit.

Integrating formal verification and high-level processor pipeline synthesis

“…Existing high-level design frameworks (e.g., [11][13] [15]) provides correct-by-construction property, but do not have integrated formal verification to ensure the correctness of the output implementation that it generates. Thus, they are prone to aforesaid "programming" and "algorithmic" bugs.…”

“…The need to apply a high-degree of customization within a short time-to-market makes it intractable to develop application-specific processors (ASIPs) manually. To address this, prior works (e.g., [11][13] [15]) have presented design frameworks that can be used to automatically synthesize custom pipelined processor implementations (usually at the register transfer level) from a precise high-level specification. These frameworks drastically shorten the time to arrive at an implementation.…”

Optimizing sequential cycles through Shannon decomposition and retiming

“…Hassoun and Ebeling's [10] architectural retiming mixes retiming with speculation and prediction to optimize pipelines; Marinescu and Rinard's technique [11] proposes using stalling and forwarding. Like us, they identify critical cycles as a major performance issue, but they synthesize from high-level specifications and can make architectural decisions.…”

Task Partitioning for Multi-core Network Processors

“…Our work has more in common with Hardware Pipelining [16,19]: the division of a circuit specification into concurrent pipeline stages such that each stage is of roughly uniform size. However, unlike our work, the successive stages run in lock-step with no queueing between them-a model which is inappropriate for packet processing systems.…”