Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out

Seong, Nak Hee; Woo, Dong Hyuk; Lee, Hsien-Hsin

doi:10.1109/mm.2010.101

Cited by 20 publications

(15 citation statements)

References 7 publications

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“…The start-gap algorithm is extended in [16] to an online attack detector, which dynamically adjusts the frequency of start-gap by monitoring suspicious memory write patterns. Furthermore, both [3] and [17] propose schemes to randomly swap the memory addresses of data blocks, to protect memory against malicious wear out attacks.…”

Section: Pcm Security Enhancementsmentioning

confidence: 99%

Secure and Durable (SEDURA)

Liu

Yang

2015

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM

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Phase changing memory (PCM) is considered a promising candidate for next-generation main-memory. Despite its advantages of lower power and high density, PCM faces critical security challenges due to its non-volatility: data are still accessible by the attacker even if the device is detached from a power supply. While encryption has been widely adopted as the solution to protect data, it not only creates additional performance and energy overhead during data encryption/decryption, but also hurts PCM lifetime by introducing more writes to PCM cells.In this paper, we propose a framework that integrates encryption and wear-leveling so as to mitigate the adverse impact of encryption on PCM performance and lifetime. Moreover, by randomizing the address space during wearleveling, an extra level of protection is provided to the data in memory. We propose two algorithms that respectively prioritize data security and memory lifetime, allowing designers to trade-off between these two factors based on their needs. Compared to previous encryption techniques, the proposed SEDURA framework is able to deliver both more randomness to protect data and more balanced PCM writes, thus effectively balancing the three aspects of data security, application performance, and device lifetime.

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Section: Pcm Security Enhancementsmentioning

confidence: 99%

Secure and Durable (SEDURA)

Liu

Yang

2015

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM

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“…A preSET method was proposed to enhance the performance of PCM by scheduling the SET operation before the actual write operation [10]. The security issue in PCM has been studied in [11], [12]. The security refresh approach was proposed to protect PCM against malicious wear out [11].…”

Section: Related Workmentioning

confidence: 99%

“…The security issue in PCM has been studied in [11], [12]. The security refresh approach was proposed to protect PCM against malicious wear out [11]. A low overhead method via online attack detection was designed [12].…”

Section: Related Workmentioning

confidence: 99%

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Optimizing Scheduling in Embedded CMP Systems with Phase Change Memory

Zhang

Qiu

et al. 2012

2012 IEEE 18th International Conference on Parallel and Distributed Systems

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Phase Change Memory (PCM) is emerging as one of the most promising alternative technology to the Dynamic RAM (DRAM) when building large-scale main memory systems.Even though the PCM is easy to scale, it encounters serious endurance problems. Writes are the primary wear mechanism in the PCM. The PCM can perform 10 8 to 10 9 times of writes before it cannot be programmed reliably. In addition, the PCM has high write latency. To prolong the lifetime of the PCM as the main memory and enhance the performance, we propose a Scratch Pad Memory (SPM) based memory mechanism and an Integer Linear Programming (ILP) memory activities scheduling algorithm to reduce the redundant write operations in the PCM. The idea of our approach is to share the data copies among the SPMs, instead of writing back to the PCM main memory each time a modify occurs. Our experimental results show that the ILP scheduling can generate the optimal schedule of memory activities with minimum write operations, reducing the number of write by up to 61%.

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“…However, NVMs present new challenges in comparison to DRAM: asymmetric read/write access latencies, higher power/energy requirements, and limited endurance, which impede their large-scale adoption in computing systems [1][2][3]. To overcome these problems, a broad set of solutions that rely on dataencoding [5], write scheduling [6][7][8][9], data-migration using address translation [10][11][12], and architectural improvements [13,14] have been proposed. However, these techniques address either NVM latency, power/energy, or endurance explicitly; this potentially limits their effectiveness in practice.…”

Section: Introductionmentioning

confidence: 99%

Flip-Mirror-Rotate

Palangappa

Mohanram

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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This paper proposes Flip-Mirror-Rotate (FMR), an architecture for bit-write reduction and endurance enhancement in emerging nonvolatile memories (NVMs). FMR comprises three components: adaptive Flip-N-Write (aFNW), Mirror-N-Write (MNW), and Rotate-N-Write (RNW). aFNW and MNW focus on word-level bit-write reduction, which reduces NVM dynamic energy while also improving endurance. RNW is an intra-word wear leveling scheme that operates at cache line granularity. The proposed FMR architecture is integrated with frequent pattern compression (FPC) to simultaneously reduce bit-writes and wear in NVMs. Trace-based simulations of the SPEC CPU2006 benchmarks show that for the same memory overhead and < 1% loss in memory bandwidth, FMR reduces bit-writes (dynamic energy) by 48% (29%) in comparison to classical read-modify-write (DCW), 39% (13%) in comparison to Flip-N-Write (FNW), and 21% (14%) in comparison to FPC. Simultaneously, FMR also reduces the peak bit-writes per cell by 47% in comparison to DCW, 34% in comparison to FNW, and 47% in comparison to FPC, improving NVM endurance.

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Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out

Cited by 20 publications

References 7 publications

Secure and Durable (SEDURA)

Secure and Durable (SEDURA)

Optimizing Scheduling in Embedded CMP Systems with Phase Change Memory

Flip-Mirror-Rotate

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