Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy

Xie, Yang; Bao, Chongxi; Srivastava, Ankur

doi:10.1109/mc.2017.121

Cited by 26 publications

(16 citation statements)

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“…(For our cut sizes on larger benchmarks, refer to Table 7). Regarding PPA, we observe significantly lower costs than [21]. 5 Besides, as with regular SM, their 2.5D scheme is not inherently resilient against malicious end-users, but our 3D scheme is.…”

Section: Comparison With Prior Artmentioning

confidence: 81%

“…Also, various studies are hinting at 3D integration for SM, but most have limitations or cover different scenarios. For example, Dofe et al [20] remain on the conceptional level, or Xie et al [21] and Imeson et al [10] consider 2.5D integration where only wires are hidden from the untrusted foundry. We summarize the prior art on 3D SM in Table 1, along with that for 3D LC.…”

Section: Split Manufacturingmentioning

confidence: 99%

“…In Table 6, we compare with the security-driven 2.5D integration scheme by Xie et al [21]. Their work is relevant as they propose a similar notion of security based on cut sizes.…”

Section: Comparison With Prior Artmentioning

confidence: 99%

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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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Split manufacturing (SM) and layout camouflaging (LC) are two promising techniques to obscure integrated circuits (ICs) from malicious entities during and after manufacturing. While both techniques enable protecting the intellectual property (IP) of ICs, SM can further mitigate the insertion of hardware Trojans (HTs). In this paper, we strive for the "best of both worlds," that is we seek to combine the individual strengths of SM and LC. By jointly extending SM and LC techniques toward 3D integration, an up-and-coming paradigm based on stacking and interconnecting of multiple chips, we establish a modern approach to hardware security. Toward that end, we develop a security-driven CAD and manufacturing flow for 3D ICs in two variations, one for IP protection and one for HT prevention. Essential concepts of that flow are (i) "3D splitting" of the netlist to protect, (ii) obfuscation of the vertical interconnects (i.e., the wiring between stacked chips), and (iii) for HT prevention, a security-driven synthesis stage. We conduct comprehensive experiments on DRC-clean layouts of multi-million-gate DARPA and OpenCores designs (and others). Strengthened by extensive security analysis for both IP protection and HT prevention, we argue that entering the third dimension is eminent for effective and efficient hardware security.

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Section: Comparison With Prior Artmentioning

confidence: 81%

Section: Split Manufacturingmentioning

confidence: 99%

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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Patnaik

Ashraf²,

Sinanoglu³

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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“…This idea serves for labelling and authentication of chips (or other goods, for that matter). Loosely related, because without [182] 2.5D IP protection; SM Interposer [82] 2.5D Trojan prevention; SM Interposer [183] F2F IP protection; SM, camouflaging Parts of 3D IC [184] M3D IP protection; camouflaging Whole 3D IC [185] F2F IP protection, Trojan prevention; Only BEOL SM, camouflaging [186] TSV Probing protection; enclosure Whole 3D IC [187,188] TSV Side-channel mitigation; enclosure Whole 3D IC [4] 2.5D Runtime monitoring; separation Interposer the need for nanowires, the authors in [93] proposed the concept of plasmonics-enhanced optical PUFs and provide physical-simulation results and a security analysis.…”

Section: Nanowires and Nwfetsmentioning

confidence: 99%

“…For example, the study [180] remains only on the conceptional level, while the studies [82,182] utilize 2.5D integration with "only" wires being hidden from untrusted facilities. The latter is in principal equivalent to traditional split manufacturing but seems more practical; still, the studies [82,182] report on considerable layout cost. Later on, [183,185,191,192] promoted "native 3D split manufacturing, " i.e., with logic being split across trusted and untrusted facilities.…”

Section: Confidentiality and Integrity Ofmentioning

confidence: 99%

Hardware Security For and Beyond CMOS Technology

Knechtel¹

2020

Proceedings of the 2020 International Symposium on Physical Design

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As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges. CCS CONCEPTS• Security and privacy → Security in hardware; • Hardware → Emerging technologies.

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Satisfiability Based Attacks

Vemuri

Chen

2021

Split Manufacturing of Integrated Circuits for Hardware Security and Trust

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Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy

Cited by 26 publications

References 0 publications

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

Hardware Security For and Beyond CMOS Technology

Satisfiability Based Attacks

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