Security Assessment of High-Level Synthesis

Muttaki, Md Rafid; Pundir, Nitin; Tehranipoor, Mark; Farahmandi, Farimah

doi:10.1007/978-3-030-64448-2_6

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…Our results demonstrate faster coverage of rare targets and more effective detection of trojans hidden in rare locations across a variety of benchmark designs compared to earlier methods. The complete GreyConE+ framework has the potential to significantly enhance the automated detection of security vulnerabilities in HLS designs [48]. The efficiency of GreyConE+ in terms of time, number of test cases, and memory requirements is highly desirable for use in cloud environments, where time, energy, and storage are valuable resources.…”

Section: Discussionmentioning

confidence: 99%

“…Existing research has predominantly focused on testing Hardware HWIPs at RTL or gate-level designs, leaving a significant gap in exploring testing methodologies at higher levels of abstraction, particularly in the context of HLS tailored for FPGA-cloud environments [48]. However, vulnerabilities at these higher abstraction levels tend to be more intricate and stealthy, especially when HLS IPs contain malicious functionalities like hidden trojan logic, which can pose substantial risks to cloud environments by leaking sensitive information and tampering with cloud computation and data.…”

Section: Motivationmentioning

confidence: 99%

“…Therefore, verifying the security aspects of HLS IPs is crucial for CSPs to ensure accurate functionality. [8] Gate level ATPG binning + SAT formulation ISCAS85, ISCAS89, ITC99 ✗ Huang et al [28] Gate level Guided ATPG ISCAS85, ISCAS89 ✗ Liu et al [45] Gate level Genetic algorithm + SMT formulation TrustHub [55] ✗ Ahmed et al [5] Register transfer level Concolic testing TrustHub [55] ✓ Ahmed et al [4] Register Transfer Level Greedy concolic testing TrustHub [55] ✓ Lyu et al [44] Register Transfer Level Parallelism + concolic testing TrustHub [55] ✓ Veerana et al [58] HLS/SystemC Property checking S3C [59] ✓ Le et al [36] HLS/SystemC Guided greybox fuzzing S3C [59] ✗ Bin et al [38] HLS/SystemC Selective concolic testing S3C [59] ✗ Vafaei et al [57] C-level(from RTL) Symbolic Execution TrustHub [55] ✓ GreyConE [19] HLS/SystemC,C/C++ Greybox Fuzzing(GF) + Concolic Execution(CE) S3C [59],S2C [51] ✗ GreyConE+(Ours) HLS/SystemC,C/C++ Selective Instrumentation with GF + CE S3C [59], S2C [51],SC [40],Rosetta [66] ✓ functionalities like Trojans in IP designs introduces potential threats, including the risk of IP malfunctions, leakage of sensitive information, and potential damage to underlying hardware [48,58]. Vulnerabilities within third party HLS IPs might arise during the design phase, presenting similarities to security challenges encountered in untrusted electronics supply chains and the insertion of Trojans in pre-silicon hardware.…”

Section: Introductionmentioning

confidence: 99%

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GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs

Debnath

Chowdhury

Saha

et al. 2022

2022 IEEE International Test Conference (ITC)

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High-Level Synthesis (HLS) has transformed the development of complex Hardware IPs (HWIP) by offering abstraction and configurability through languages like SystemC/C++, particularly for Field Programmable Gate Array (FPGA) accelerators in high-performance and cloud computing contexts. These IPs can be synthesized for different FPGA boards in cloud, offering compact area requirements and enhanced flexibility. HLS enables designs to execute directly on ARM processors within modern FPGAs without the need for Register Transfer Level (RTL) synthesis, thereby conserving FPGA resources. While HLS offers flexibility and efficiency, it also introduces potential vulnerabilities such as the presence of hidden circuitry, including the possibility of hosting hardware trojans within designs.In cloud environments, these vulnerabilities pose significant security concerns such as leakage of sensitive data, IP functionality disruption and hardware damage, necessitating the development of robust testing frameworks. This research presents an advanced testing approach for HLS-developed cloud IPs, specifically targeting hidden malicious functionalities that may exist in rare conditions within the design. The proposed method leverages selective instrumentation, combining greybox fuzzing and concolic execution techniques to enhance test generation capabilities. Evaluation conducted on various HLS benchmarks, possessing characteristics of FPGA-based cloud IPs with embedded cloud related threats, demonstrates the effectiveness of our framework in detecting trojans and rare scenarios, showcasing improvements in coverage, time efficiency, memory usage, and testing costs compared to existing methods.

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Section: Discussionmentioning

confidence: 99%

Section: Motivationmentioning

confidence: 99%