Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations

Fiorin,; Silvano, Cristina; Sami,

doi:10.1109/dsd.2007.4341520

Cited by 47 publications

(49 citation statements)

References 7 publications

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“…The Network-on-Chips (NoCs) [6,8] concept has proven itself as a solid interconnection strategy that brings reliable, efficient and fast intercore communication. However, managing communication in modern embedded systems necessarily carries many security challenges related to the secure transfer and storage of critical data [13]. In fact, enabling a secure communication among the rapidly growing number of integrated IP cores is a task becoming more and more relevant.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, there is an increased need of security-aware design solutions, in particular in the design of reconfigurable SoCs. However, even if the research on NoC related topics has been an emerging area of interest, security issues in this field have been often shadowed by other topics and not been explored to the same extent, being only recently addressed by the research community [13,11].…”

Section: Introductionmentioning

confidence: 99%

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Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Fiorin

Luković

Palermo³

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Fiorin

Luković

Palermo³

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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“…For example, we would like to extend our drawbridge model to support Networks-on-Chip (NoCs) to provide efficient and secure communication among many cores. There are several open research questions in the design of NoCs, and techniques for incorporating security into the design of NoCs by enhancing the network interface are starting to emerge [Diguet et al 2007;Florin et al 2007a;2007b].…”

Section: Resultsmentioning

confidence: 99%

Security Primitives for Reconfigurable Hardware-Based Systems

Huffmire

Levin

Nguyen

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

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Computing systems designed using reconfigurable hardware are increasingly composed using a number of different Intellectual Property (IP) cores, which are often provided by third-party vendors that may have different levels of trust. Unlike traditional software where hardware resources are mediated using an operating system, IP cores have fine-grain control over the underlying reconfigurable hardware. To address this problem, the embedded systems community requires novel security primitives that address the realities of modern reconfigurable hardware. In this work, we propose security primitives using ideas centered around the notion of "moats and drawbridges." The primitives encompass four design properties: logical isolation, interconnect traceability, secure reconfigurable broadcast, and configuration scrubbing. Each of these is a fundamental This research was funded in part by National Science Foundation Grant CNS-0524771, NSF Career Grant CCF-0448654, and the SMART Defense Scholarship for Service. Authors' addresses: T. Huffmire, T. Levin, T. Nguyen, and C. Irvine, Department of Computer Science, Naval Postgraduate School, Monterey, CA 93943; email: {tdhuffmi, televin, tdnguyen, irvine}@nps.edu; B. Brotherton, Special Technologies Laboratory, Santa Barbara, CA 93111; email: brett.brotherton@gmail.com; G. Wang, Intuit, San Diego, CA 92122; email: Gang Wang@ intuit.com; T. Sherwood, Department of Computer Science, University of California, Santa Barbara, CA 93106; email: sherwood@cs.ucsb.edu; R. Kastner, Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA 92093; email: kastner@cs.ucsd.edu. c 2010 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by a contractor or affiliate of the [U.S.] Government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212) operation with easily understood formal properties, yet they map cleanly and efficiently to a wide variety of reconfigurable devices. We carefully quantify the required overheads of the security techniques on modern FPGA architectures across a number of different applications.

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“…Our work can be considered similar in some concepts to [10], in which link utilization is monitored to implement a strategy for controlling congestion in on-chip networks, or [11] and [12], where monitoring of NoCs to detect security violations in suggested. However, we differentiate from [10], [11], [12] in the fact that we propose …”

Section: Related Workmentioning

confidence: 99%

MPSoCs run-time monitoring through Networks-on-Chip

Fiorin

Palermo

Silvano

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper, we discuss the idea of using NoCs to monitor system behaviour at run-time by tracing activities at initiators and targets. Main goal of the monitoring system is to retrieve information useful for run-time optimization and resources allocation in adaptive systems. Information detected by probes embedded within NIs is sent to a central unit, in charge of collecting and elaborating the data. We detail the design of the basic blocks and analyse the overhead associated with the ASIC implementation of the monitoring system, as well as discussing implications in terms of the additional traffic generated in the NoC 1 .

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Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations

Cited by 47 publications

References 7 publications

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Security Primitives for Reconfigurable Hardware-Based Systems

MPSoCs run-time monitoring through Networks-on-Chip

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