High-capacity FPGAs pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, clock distribution and IO capacity. This paper describes these problems and the solutions to these problems chosen in the Xilinx XC4000EX family architecture.
OverviewXC4000EX family of devices extends the architecture of the XC4000 [Hsieh 1990][Trimberger 1994] to larger gate counts. Devices have been announced with over 2300 CLBs and nearly 7000 LUTs. The XC4000EX CLB is compatible with the XC4000E, leveraging eight years of applications and software development. The XC4000EX includes additions and extensions for high-capacity devices [Xilinx 1996].The basic tiled structure of the XC4000 devices is shown in figure 1. We increased the logic capacity of the family by building larger array sizes, without changing the CLB structure or removing interconnect or switches. By limiting changes to interconnect additions, the XC4000EX arrays are backward-compatible with existing XC4000 and XC4000E designs (though the devices are not bitstream-compatible). Changes in the I/O block were also made as backward-compatible improvements. Therefore existing XC4000 family logic block cores can be easily ported to the XC4000EX. This paper addresses three major architectural issues we resolved when making large devices:Interconnect. Larger devices require proportionally more interconnect. If the device does not have enough interconnect to support the logic, then some logic will go unused, limiting the capacity of the device, defeating the purpose of building large-capacity devices. When scaling an FPGA architecture to larger capacity, additional interconnect must be added to allow those devices to be routed efficiently.Clocking. FPGAs typically provide low-skew global clock signals. Low-skew is achieved fundamentally by slowing down fast clock paths to be as slow as the slowest path. On a very large device, the de-skewing circuitry may incur a severe performance penalty for a clock that is only required at the periphery, but is delayed to avoid skew over the whole chip. This delay shows as long clock-to-out times and long input setup times or (worse) non-zero hold times on inputs.
I/O.Integrated circuit process feature size is shrinking much faster than minimum pad spacing. Further, the number of X3712 CLB