Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs

Britton, B.K.; Oh, Y.T.; Oswald, William; Nguyen, Huy; Singh, Satwant; Lee, G.; Leung, W.-B.; Spivak, C.; Steward, J.; Chen, C.T.

doi:10.1109/asic.1994.404516

Cited by 10 publications

(9 citation statements)

References 7 publications

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“…Another important improvement to the architecture generator described in this work would be to allow the automatic generation of heterogeneous FPGAs -that is, FPGAs with several different types of routing channels, or several different types of function blocks. For example, the Lucent Orca FPGAs contain two different types of routing channels [17], while many commercial FPGAs contain two different types of function blocks: logic blocks and RAM blocks.…”

Section: Discussionmentioning

confidence: 99%

Automatic generation of FPGA routing architectures from high-level descriptions

Betz

Rose

2000

Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays

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In this paper we present a "high-level" FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. We then present an "architecture generator" built into the VPR CAD tool [1, 2] that converts this high-level architecture description into a detailed and completely specified flat FPGA architecture. This flat architecture is the representation with which CAD optimization and visualization modules typically work. By allowing FPGA researchers to specify an architecture at a high-level, an architecture generator enables quick and easy "what-if" experimentation with a wide range of FPGA architectures. The net effect is a more fully optimized final FPGA architecture. In contrast, when FPGA architects are forced to use more traditional methods of describing an FPGA (such as the manual specification of every switch in the basic tile of the FPGA), far less experimentation can be performed in the same time, and the architectures experimented upon are likely to be highly similar, leaving important parts of the design space completely unexplored. This paper describes the automated routing architecture generation problem, and highlights the two key difficulties -creating an FPGA architecture that matches all of an FPGA architect's specifications, while simultaneously determining good values for the many unspecified portions of an FPGA so that a high quality FPGA results. We describe the method by which we generate FPGA routing architectures automatically, and present several examples.

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Section: Discussionmentioning

confidence: 99%

Automatic generation of FPGA routing architectures from high-level descriptions

Betz

Rose

2000

Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays

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“…The Lucent Technologies ORCA 2C FPGAs employ a non-uniform routing architecture of this type, in which the center channel is wider than the others [6]. On the other hand, board-level constraints often force designers to fix the position of an FPGA's I/Os, and some believe that this increases congestion near the chip edges, and therefore the channel between the pads and the logic block array should be widened.…”

Section: Introductionmentioning

confidence: 99%

Effect of the prefabricated routing track distribution on FPGA area-efficiency

Betz

Rose

1998

IEEE Trans. VLSI Syst.

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“…Theoretical efforts were pioneered by Heller [1978], Donath [1979] and El Gamal [1981], and used recently by Britton [1994]. Predictions from theoretical models are very sensitive to few exponential parameters in those models (i.e.…”

Section: Interconnectmentioning

confidence: 99%

“…This critical issue is easily ignored, particularly when using theoretical models of routability. One option would be to collect additional interconnect into new large wiring channel in the center of the device [Britton 1994]. Intuitively, this would impose an additional burden on the existing interconnect to route longdistance signals to those large wiring channels, then from the channel to their destinations.…”

Section: Interconnect Locationmentioning

confidence: 99%

“…For evaluation of the XC4000EX interconnect, we used theoretical methods of El Gamal[1981] and Britton[1994] to get a rough estimate the interconnect required, followed by the empirical method to choose the channel segmentation and to fine-tune the number of interconnect lines. The designs we used were chosen from ten ASIC designs from our industrial partners.…”

Section: Interconnectmentioning

confidence: 99%

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Architecture issues and solutions for a high-capacity FPGA

Trimberger

Duong

Conn

1997

Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays - FPGA '97

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High-capacity FPGAs pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, clock distribution and IO capacity. This paper describes these problems and the solutions to these problems chosen in the Xilinx XC4000EX family architecture. OverviewXC4000EX family of devices extends the architecture of the XC4000 [Hsieh 1990][Trimberger 1994] to larger gate counts. Devices have been announced with over 2300 CLBs and nearly 7000 LUTs. The XC4000EX CLB is compatible with the XC4000E, leveraging eight years of applications and software development. The XC4000EX includes additions and extensions for high-capacity devices [Xilinx 1996].The basic tiled structure of the XC4000 devices is shown in figure 1. We increased the logic capacity of the family by building larger array sizes, without changing the CLB structure or removing interconnect or switches. By limiting changes to interconnect additions, the XC4000EX arrays are backward-compatible with existing XC4000 and XC4000E designs (though the devices are not bitstream-compatible). Changes in the I/O block were also made as backward-compatible improvements. Therefore existing XC4000 family logic block cores can be easily ported to the XC4000EX. This paper addresses three major architectural issues we resolved when making large devices:Interconnect. Larger devices require proportionally more interconnect. If the device does not have enough interconnect to support the logic, then some logic will go unused, limiting the capacity of the device, defeating the purpose of building large-capacity devices. When scaling an FPGA architecture to larger capacity, additional interconnect must be added to allow those devices to be routed efficiently.Clocking. FPGAs typically provide low-skew global clock signals. Low-skew is achieved fundamentally by slowing down fast clock paths to be as slow as the slowest path. On a very large device, the de-skewing circuitry may incur a severe performance penalty for a clock that is only required at the periphery, but is delayed to avoid skew over the whole chip. This delay shows as long clock-to-out times and long input setup times or (worse) non-zero hold times on inputs. I/O.Integrated circuit process feature size is shrinking much faster than minimum pad spacing. Further, the number of X3712 CLB

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Second generation ORCA architecture utilizing 0.5 μm process enhances the speed and usable gate capacity of FPGAs

Cited by 10 publications

References 7 publications

Automatic generation of FPGA routing architectures from high-level descriptions

Automatic generation of FPGA routing architectures from high-level descriptions

Effect of the prefabricated routing track distribution on FPGA area-efficiency

Architecture issues and solutions for a high-capacity FPGA

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