SecChisel Framework for Security Verification of Secure Processor Architectures

Deng, Sier; Gümüşoğlu, Doğuhan; Xiong, Wenjie; Sari, Sercan; Gener, Y. Serhan; Lu, Corine; Demir, Onur; Szefer, Jakub

doi:10.1145/3337167.3337174

Cited by 11 publications

(6 citation statements)

References 19 publications

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“…The SecVerilog tool has been extended to support mutable dependent types to solve the implicit downgrading problem [284] and the chisel HDL. SecChisel [285] can be used to create secure architectures, synthesize secure cryptographic accelerators and capture information leaks caused by hardware security flaws, timing channels and HTs through type checking.…”

Section: Hardware Security Tools a Security Verification Toolsmentioning

confidence: 99%

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Hardware Security Tools a Security Verification Toolsmentioning

confidence: 99%

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Chang

Sengupta

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Formal methods are required in this process. For example, information flow tracking, such as methods in [24,115,116], can be used to analyze the hardware components, where the data of transient execution could flow to. Then, analyze if each of the components could result in a permanent or transient covert channel.…”

Section: Mitigating Covert Channelsmentioning

confidence: 99%

Survey of Transient Execution Attacks

Xiong

Szefer

2020

Preprint

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Transient execution attacks, also called speculative execution attacks, have drawn much interest as they exploit the transient execution of instructions, e.g., during branch prediction, to leak data. Transient execution is fundamental to modern computer architectures, yet poses a security risk as has been demonstrated. Since the first disclosure of Spectre and Meltdown attacks in January 2018, a number of new attack types or variants of the attacks have been presented. These attacks have motivated computer architects to rethink the design of processors and propose hardware defenses. This paper summarizes the components and the phases of the transient execution attacks. Each of the components is further discussed and categorized. A set of metrics is proposed for each component to evaluate the feasibility of an attack. Moreover, the data that can be leaked in the attacks are summarized. Further, the existing attacks are compared, and the limitations of these attacks are discussed based on the proposed metrics. In the end, existing mitigations at the micro-architecture level from literature are discussed.

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“…Besides, manual analysis and associating the probability to hardware behaviors can lead to incomprehensive conclusions. (4) New hardware description languages (HDL) were introduced to design secure hardware circuits [6,16,36] with formal proof. These solutions are not comprehensive for side-channel analysis: they can only be applied to the partitioning-based caches while failing to evaluate the randomization-based designs with stochastic behaviors.…”

Section: Introductionmentioning

confidence: 99%

A Formal Methodology for Verifying Side-Channel Vulnerabilities in Cache Architectures

Jiang

Zhang

Sanán

et al. 2022

Formal Methods and Software Engineering

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Security-aware CPU caches have been designed to mitigate side-channel attacks and prevent information leakage. How to validate the effectiveness of these designs remains an unsolved problem. Prior works assess the security of architectures empirically without a formal guarantee, making the evaluation results less convincing. In this paper, we propose a comprehensive methodology based on formal methods for security verification of cache architectures. Specifically, we design an entropy-based noninterference reasoning framework with two unwinding conditions to assess the information leakage of the cache designs. The reasoning framework quantifies the dependency relationships by the mutual information between the distributions of input and output of side channels. Given a cache design, we formalize its behavior specification along with the cache layouts into an abstract state machine, to instantiate the parameterized reasoning framework that discloses any potential vulnerabilities. We use our methodology to assess eight state-of-the-art cache architectures to demonstrate reliability as well as flexibility.

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SecChisel Framework for Security Verification of Secure Processor Architectures

Cited by 11 publications

References 19 publications

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

Survey of Transient Execution Attacks

A Formal Methodology for Verifying Side-Channel Vulnerabilities in Cache Architectures

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