SCR-Based ESD Protection Using a Penta-Well for 5 V Applications

Song, Bo-Bae; Do, Kyoung-Il; Koo, Yong-Seo

doi:10.1109/jeds.2018.2817636

Cited by 27 publications

(11 citation statements)

References 7 publications

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“…As the length of L2 increases, more electrons are recombined in the base region of the NPN parasitic bipolar transistor. Therefore, the holding voltage of the silicon carbide lateral SCR is increased because it increases the emitter injection efficiency of the NPN parasitic bipolar transistor [12]. Also, when compared to L1, L2 is a P + implant region and has a higher doping concentration.…”

Section: Tlp Measurementmentioning

confidence: 99%

A Fabrication of 4H-Silicon Carbide Based-Lateral SCR for ESD Protection Device

Do¹,

Park²

2019

IJAST

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This paper demonstrates a silicon carbide-based lateral silicon controlled rectifier (SCR) for use as an electrostatic discharge (ESD) protection device for high current ICs mounted on EVs or self-driving vehicles. The protection devices were designed with three split items and were fabricated with a line width of 0.5 µm. The protection devices were verified in terms of their electrical characteristics by using a transmission line pulse (TLP) system and a curve tracer. The measurements indicate that the devices have a trigger voltage of 165 V and a holding voltage of 40 V. The lateral SCR devices have a breakdown voltage (BV) of 82 V. In addition, the second breakdown current of the demonstrated SCR is above 18 A.

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Section: Tlp Measurementmentioning

confidence: 99%

A Fabrication of 4H-Silicon Carbide Based-Lateral SCR for ESD Protection Device

Do¹,

Park²

2019

IJAST

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“…Conventional diode structures and Gate-Grounded NMOS (GGNMOS) structures always require a large silicon area to achieve a good ESD robustness [7][8][9][10]. By contrast, silicon controlled rectifiers (SCRs) have been widely used due to their highest robustness per unit area [11][12][13][14][15][16][17][18][19][20]. However, the unique positive feedback loop of the SCR structure makes it have deep snapback characteristics, which cause a low holding voltage.…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

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The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

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“…By providing an additional ESD discharge path, the recently proposed low-dynamic -resistance-dual SCR (LDRDSCR) [5] has an excellent dynamic resistance. However, its low holding voltage falls outside the high-voltage ESD design window, and the device structure must be lengthened, increasing its on-resistance [8][9][10]. Fig.…”

Section: Introductionmentioning

confidence: 99%

A Novel Low Dynamic Resistance Dual-Directional SCR with High Holding Voltage for 12 V Applications

Koo

2020

IEEE J. Electron Devices Soc.

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The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high holding voltage and low dynamic resistance is proposed and its electrical characteristics are verified. The proposed DDSCR has two additional internal parasitic bipolar transistors compared to a conventional lowtriggering voltage DDSCR (LTDDSCR). Self-gate biasing reduces latch-mode feedback between the parasitic bipolar transistors in the SCR. The device is fabricated using 0.13 um BCD processes and implements a segment layout resulting in a very low dynamic resistance of 2.2 Ω and excellent holding voltages of up to 17.2 V. The proposed DDSCR demonstrates improved reliability and area efficiency for 12 V applications.

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SCR-Based ESD Protection Using a Penta-Well for 5 V Applications

Cited by 27 publications

References 7 publications

A Fabrication of 4H-Silicon Carbide Based-Lateral SCR for ESD Protection Device

A Fabrication of 4H-Silicon Carbide Based-Lateral SCR for ESD Protection Device

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

A Novel Low Dynamic Resistance Dual-Directional SCR with High Holding Voltage for 12 V Applications

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