Five‐stage CMOS OTAfrequency compensated via nested differential feedback

Abstract

Nowadays cascode structures or vertical arrangements of MOSFETs can not satisfy demands regarding high gain amplifiers. As a direct result, the only promising choice turns to Multi-stage amplifiers via cascading gain stages. The challenge here is stability issues which shows itself by different frequency compensation. All problem starts with increasing number of nodes and consequent poles. The poles degenerate phase of system and need to be controlled. In this work, a five-stage amplifier is targeted for a new and efficient frequency compensation technique. The major contribution of proposed approach is using only two Miller capacitors with considerable small values (10 pF) compared to load capacitor (500 pF). This achieved via exploiting two differential active stages which intensify Miller effect and provide capability to share Miller capacitor at multiple loops simultaneously. The proposed amplifier with corresponding frequency compensation is described symbolically while a circuit level implementation is performed via HSPICE circuit simulator and TSMC 0.18 μm CMOS technology. Based on simulation results, the proposed amplifier expresses a DC gain of 195 dB, a gain bandwidth product of 15.2 MHz, a phase margin of 90 , and a power dissipation of 570 μW.

Four stage CMOS operational amplifier, frequency compensated via active miller network

“…After those choices, the input pair dominates the noise contribution of both types. From Equation (30), the charge of the input pair's gate length can increase or decrease the flicker noise 16 …”

“…Solving these equations against node voltages reveals TF symbolically as described by Equation (7) with the three conditions that assumed larger than unity for each stage DC gain, a larger value for load capacitor compared to compensation capacitors, and smaller values for parasitic capacitors in comparison of Miller capacitors. The simplifier coefficients are reported by Equations ( 8)- (16).…”

“…From Equation (30), the charge of the input pair's gate length can increase or decrease the flicker noise. 16 F I G U R E 6 GBW and PM deviations versus differential blocks transconductances.…”

“…The main drawback of NMC and RNMC is needing large-value Miller capacitors. 15,16 For instance, almost a larger than 100 pF compensation capacitor is required for a 100 pF load capacitor. This limitation may satisfy designers to consider compensation capacitors off-chip.…”

“…These two methods, perform frequency compensation via two Miller loops. The main drawback of NMC and RNMC is needing large‐value Miller capacitors 15,16 . For instance, almost a larger than 100 pF compensation capacitor is required for a 100 pF load capacitor.…”