DC and RF /analog parameters in Ge‐source split drain ‐ZHP‐TFET : Drain and pocket engineering technique

In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG) nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap sensitivity is extracted for Gaussian trap distribution of both acceptor and donor type traps. We have reported the trap sensitivity for the variation in trap concentration, energy peak position, work function of metal gate, and temperature for both the NRFETs. It is realized that trap sensitivity is greater and lesser than 100% for acceptor type trap in SMG and DMG NRFETs, respectively, whereas, such sensitivity is 147% and 123% for donor type trap concentration, respectively. Temperature also shows a significant variation in trap sensitivity for both the NRFETs. The increase in work function leads to the reduction in trap sensitivity for both NRFETs in existence of acceptor and donor trap charges. The maximum sensitivity in trap are 400% and 275% for SMG and DMG NRFETs, respectively, in presence of donor trap concentration. Moreover, the trap sensitivity is very insignificant at high gate bias for donor type trap concentration with wide variation in parameters.

Section: Resultsmentioning

confidence: 99%

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Rai,

Sharma,

Saha

et al. 2024

“…To date, the efficiency of CZTSe solar cells is reported as 12.6% under AM 1.5 spectrum [2] and can be reached up to 32.2%, which is very high compared to the reported efficiency [3,4]. So to improve the performance of CZTS solar cell lot of experimental and theoretical studies have been reported so far [5][6][7].…”

Section: Introductionmentioning

confidence: 98%

Improving the efficiency of ZnO/WS₂/CZTS1 solar cells using CZTS2 as BSF layer by SCAPS-1D numerical simulation

Dakua¹,

Panda

2023

Self Cite

With a high absorption coefficient and tunable bandgap CZTS (Copper Zinc Tin Sulfide) makes it suitable for photovoltaic applications. Present paper deals with the simulation and modeling of CZTS-based solar cells using tungsten disulfide (WS2) as the buffer layer and CZTS2 as the back surface field (BSF) layer to study the performance of the solar cell. Considering different physical and geometrical parameters such as thickness, acceptor density, interfacial defect density, and metal contact work functions the device calibration has been done. The temperature is varied from 300 K to 400 k to study the impact on device performance. The C-V and 1/C2 plot is presented to calculate the built-in voltage for the device. The series (Rs) and shunt (Rsh) resistance of 1 and 106 ohm.cm2 were kept throughout the simulation. The optimized thickness for the absorber, BSF, buffer, and window layers are 800 nm, 140 nm, 30 nm, and 90 nm respectively. The obtained results are validated using the experimental results available in the literature. Varying the values of different parameters, the optimal efficiency of 26 % was reported in this work. Contrary to conventional solar cells, which contain expensive and toxic elements, WS2 may be a good option as a buffer layer in CZTS solar cells.

“…Bottom side of gate provides immunity against reverse leakage current in a regular manner. As a result, the simulated device is described as the Z-shape horizontal pocket line TFET analogical to the oxide structure in Z-shape [15][16][17][18][19][20]. A high-k oxide (HfO 2 ) layer is placed over the source area in ZHP TFETs, while a thin film of silicon dioxide (SiO 2 ) is placed on the back side of the gate.…”

Section: Introductionmentioning

confidence: 99%

Trap sensitivity of splitted source Z Shape horizontal pocket and hetero stack TFETs: a simulation study

Tiwari¹,

Saha²

2023

This paper reports the trap sensitivity analysis of split source horizontal pocket Z shape tunnel field effect transistor (ZHP-TFET) and hetero stack TFET (HS-TFET) using technology computer aided design (TCAD) simulator. The sensitivity analysis elaborates the significance of ideal trap charges at the interface of oxide and semiconductor material for both acceptor and donor like traps. The trap sensitivity analysis is highlighted for variation in trap-concentrations, temperature, gate-metal work function, and peak energy position, for both the TFETs. Furthermore, we have implemented digital inverter on taking into account the interface trap charges effect. Result reveals that tarp sensitivity on various electrical parameter of HS-TFET is significantly higher than ZHP-TFET. It is seen that ZHP-TFET provides sensitivity around 11 and 33 under acceptor and donor impurities, respectively, whereas, for HS-TFET sensitivity is around 22 and 60 for acceptor and donor impurities, respectively, for wide variation in trap concentration. The voltage transfer characteristic and voltage gain of digital inverter are improved by observable amount in ZHP-TFET than HS-TFET for both donor and acceptor like trap. The noise margin of ZHP-TFET based resistive inverter comes 0.75 V, 0.73 V, and 0.77 V, while in case of HS-TFET these value noted as 0.32 V, 0.13 V and 0.37 V under consideration for no trap, acceptor trap, and donor trap, respectively.