2021
DOI: 10.1002/jnm.2895
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CNTFET‐based active grounded inductor using positive and negative current conveyors and applications

Abstract: In this work, we design and simulate novel 32 nm carbon nanotube field effect transistor (CNTFET) as well as complementary metal oxide semiconductor (CMOS)‐based negative class AB second generation current conveyors (CC) (CNTFET‐CCII and CMOS‐CCII−). The comparative analyses of various performance measuring parameters of both these CCII's have been performed. A significant improvement in current and voltage bandwidths, terminal X and Y impedances at lesser total harmonic distortions and reduced power consumpti… Show more

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Cited by 10 publications
(7 citation statements)
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References 37 publications
(64 reference statements)
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“…It is approximately between −0.15 to +0.15 V for CMOS‐DO‐CCII and −0.5 to +0.5 V for the CNTFET‐DO‐CCII as shown in Figure 6. The larger linearity range in the proposed CNTFET‐DO‐CCII attributed to better differential pair matching of CNTFETs, M1, M2, M5, and M6, along with the unity aspect ratio in the CNTFET‐DO‐CCII 22,27,28 …”
Section: Results and Comparative Analysis Of Proposed Cmos‐do‐ccii An...mentioning
confidence: 99%
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“…It is approximately between −0.15 to +0.15 V for CMOS‐DO‐CCII and −0.5 to +0.5 V for the CNTFET‐DO‐CCII as shown in Figure 6. The larger linearity range in the proposed CNTFET‐DO‐CCII attributed to better differential pair matching of CNTFETs, M1, M2, M5, and M6, along with the unity aspect ratio in the CNTFET‐DO‐CCII 22,27,28 …”
Section: Results and Comparative Analysis Of Proposed Cmos‐do‐ccii An...mentioning
confidence: 99%
“…Both the BWs increase as D CNT increases. This is be attributed to the decrease in threshold voltage, which in turn increases the drive current of a CNTFET and hence the BWs 28 . Similarly, the X and Y port resistances decrease as D CNT increases, as shown in Figure 13C,D.…”
Section: Optimization Of Cntfet Parameters For Optimizing the Perform...mentioning
confidence: 87%
“…It is to be noted that FDFAPF circuits proposed in the technical literature [4,16,17,[19][20][21][22][23][24][25] utilize bulk semiconductor technology which faces several emerging issues due to continuous focus on device scaling in nano meter scale for further validation of Moore's law. These includes short channel effects, lithographic limitations, gate leakage, boron penetrations, high field effects, poly-silicon depletion and increased heat production etc [26,27]. There is an essential requirement to substitute the conventional bulk semiconductor technology with more reliable and robust circuit technology to work equally well at nanoscale.…”
Section: Introductionmentioning
confidence: 99%
“…Various devices architecture has been introduced recently, like CNTFET, FinFETs, double gate FET, strained Si FET etc [28]. Among these solutions, CNTFET is considered as a promising alternative for future extension of Moore's law due to its efficient electrostatic control, ballistic transport of charge carriers, large thermal conductivity, lesser parasitics, higher cutoff frequency, large drive current and low power dissipation to name a few [26][27][28]. Since introduction of CNTFET as an emerging device and better alternative of bulk semiconductor technology, limited work on CNTFET based circuit design has been carried out in analog filtering domain [10,18,26,27,29,30].…”
Section: Introductionmentioning
confidence: 99%
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