Schottky Source/Drain Ge Metal–Oxide–Semiconductor Field-Effect Transistors with Directly Contacted TiN/Ge and HfGe/Ge Structures

140

112

CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today's CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices practically viable, we need to understand why electron mobility is severely degraded in the inversion layer in Ge n-channel MOSFETs and to find out how it can be increased. In the Si CMOS technology, the SiO 2 /Si interface has long been investigated and cannot be ignored even after the introduction of high-k gate stack technology. In that sense, the GeO 2 /Ge interface should be intensively studied to make the best of Ge's advantages. Therefore we first discuss the GeO 2 /Ge interface with regard to its physical and electrical characteristics. When we regard Ge as a channel material beyond Si for high performance ULSIs, we also have to seriously consider the gate stack scalability and reliability. The source/ drain engineering, as well as the gate stack formation, is another challenge in Ge MOSFET design. Both the higher metal/Ge contact resistance and the larger p/n junction leakage current may be the consequences of Ge's intrinsic properties because they are derived from the strong Fermilevel pinning and the narrow energy band gap, respectively. Even if the...

Section: Metal Source/drain Fetmentioning

confidence: 96%

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

Toriumi

Nishimura

2017

140

112

“…Using this contact technique, we demonstrated p-MOSFET operations. 10,11) However, there were two drawbacks of the use of the HfGe=Ge contact. 12) The first one is that the HfGe film was prone to oxidation during processing.…”

mentioning

confidence: 99%

Fabrication of PtGe/Ge contacts with high on/off ratio and its application to metal source/drain Ge p-channel MOSFETs

Nagatomi

Tanaka

Nagaoka

et al. 2015

We study the level spacing distribution p(s) in the spectrum of random networks. According to our numerical results, the shape of p(s) in the Erdős-Rényi (E-R) random graph is determined by the average degree k and p(s) undergoes a dramatic change when k is varied around the critical point of the percolation transition, k = 1. When k 1, the p(s) is described by the statistics of the Gaussian orthogonal ensemble (GOE), one of the major statistical ensembles in Random Matrix Theory, whereas at k = 1 it follows the Poisson level spacing distribution. Closely above the critical point, p(s) can be described in terms of an intermediate distribution between Poisson and the GOE, the Brodydistribution. Furthermore, below the critical point p(s) can be given with the help of the regularized Gamma-function. Motivated by these results, we analyse the behaviour of p(s) in real networks such as the internet, a word association network and a protein-protein interaction network as well. When the giant component of these networks is destroyed in a node deletion process simulating the networks subjected to intentional attack, their level spacing distribution undergoes a similar transition to that of the E-R graph.

“…[231][232][233] Recent intensive studies on controlling and reducing the SBH against n-Ge as well as doping technologies of high concentration donors into Ge are expected to lead to further reduction in the S=D parasitic resistance of Ge n-MOSFETs. 39,[234][235][236][237][238][239][240][241]…”

Section: Cmos Devices Using Ge/iii-v Materialsmentioning

confidence: 99%

III–V/Ge channel MOS device technologies in nano CMOS era

Takagi

Zhang

Suh

et al. 2015

CMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.