Scheduling with integer time budgeting for low-power optimization

Zhang, Zhiru; Potkonjak, Miodrag; Cong, Jason

doi:10.1109/aspdac.2008.4483947

Cited by 14 publications

(12 citation statements)

References 13 publications

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“…Please note that other optimization objectives can still be accommodated in this formulation such as area [14] and power [11,20].…”

Section: Problem Formulationmentioning

confidence: 98%

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Register pressure aware scheduling for high level synthesis

Beidas¹,

Mong²,

Zhu³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Variations of list scheduling became the de-facto standard of scheduling straight line code in software compilers, a trend faithfully inherited by high-level synthesis solutions. Due to its nature, list scheduling is oblivious of the tightly coupled register pressure; a dangling fundamental problem that has been attacked by the compiler community for decades, and which results, in case of highlevel synthesis, in excessive instantiations of registers and accompanying steering logic.To alleviate this problem, we propose a synthesis framework called soft scheduling, which acts as a resource unconstrained prescheduling stage that restricts subsequent scheduling to minimize register pressure. This optimization objective is formulated as a live range minimization problem, a measure shown to be proportional to register pressure, and optimally solved in polynomial time using minimum cost network flow formulation. Unlike past solutions in the compiler community, which try to reduce register pressure by local serialization of subject instructions, the proposed solution operates on the entire basic block or hyperblock and systematically handles instruction chaining subject to the same objective.The application of the proposed solution to a set of real-life benchmarks results in a register pressure reduction ranging, on average, between 11% and 41% depending on the compilation and synthesis configurations with minor 2% to 4% increase in schedule latency.

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“…Please note that other optimization objectives can still be accommodated in this formulation such as area [14] and power [11,20].…”

Section: Problem Formulationmentioning

confidence: 98%

“…After performing liveness analysis on the subject method, yielding the live-in/live-out set of each block/branch (line 8), we proceed by scheduling the method's blocks one at a time (lines [10][11][12][13][14][15][16][17][18][19][20][21].…”

Section: Scheduling Flowmentioning

confidence: 99%

Register pressure aware scheduling for high level synthesis

Beidas¹,

Mong²,

Zhu³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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“…With scheduling and binding, HLS generates cycle-accurate hardware circuit from untimed behavioral description. Scheduling, the process of assigning time step to each operation, can be performed intelligently, for example, to enable additional slacks for scaling down the power for more resources [47]. Binding, the process of assigning operations to hardware resources, can likewise be performed cleverly by assigning less timing-critical operations to low-power technologies such as modules with high V th and low V DD [12], [49].…”

Section: Optimizations For Low Powermentioning

confidence: 99%

High-level Synthesis for Low-power Design

Zhang

Chen

Dai

et al. 2015

IPSJ Transactions on System LSI Design Methodology

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Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been increasingly difficult, if not already unsustainable. Complexity scaling dictates that this process must be automated with robust analysis and synthesis algorithms at a higher level of abstraction. Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. By allowing early access to the system architecture, high-level decisions during HLS can have a significant impact on the power and energy efficiency of the synthesized design. In this paper, we will discuss the recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations. We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. We will also describe the key power optimization challenges facing HLS today and outline potential opportunities in tackling these challenges.

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“…The method uses a special form of constraints in a linear program, so that it can avoid expensive branch and bound procedures in traditional ILP formulations for scheduling [10,15] while still optimizing globally. SDC is flexible enough to model a wide variety of constraints and objectives in behavioral synthesis, and is extended in [16] to solve a time budgeting problem.…”

Section: Preliminariesmentioning

confidence: 99%

Scheduling with soft constraints

Cong

Liu

Zhang³

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

Self Cite

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In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, area, power, etc., so that the resulting RTL design is favorable in these aspects. The mechanism is often flawed in practice because many such constraints are actually soft constraints which are not necessary, and the constraint system may become inconsistent when many hard constraints are added for different purposes. This paper describes a scheduler that distinguishes soft constraints from hard constraints when exploring the design space. We propose a special class of soft constraints called integer-difference soft constraints, which lead to a totally unimodular constraint matrix in an integer linear programming formulation. By exploiting the total unimodularity, the problem can be solved optimally and efficiently using a linear programming relaxation without expensive branch and bound procedures. We also show how the proposed method can be used to support a variety of design considerations. As an example application, we apply the method to the problem of low-power synthesis with operation gating. In a set of experiments on real-world designs, our method achieves an average of 33.9% reduction in total power; it outperforms a previous method by 17.1% on average and gives close-to-optimal solutions on several designs.

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Scheduling with integer time budgeting for low-power optimization

Cited by 14 publications

References 13 publications

Register pressure aware scheduling for high level synthesis

Register pressure aware scheduling for high level synthesis

High-level Synthesis for Low-power Design

Scheduling with soft constraints

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