High-level Synthesis for Low-power Design

Zhang, Zhiru; Chen, Deming; Dai, Steve; Campbell, Keith A.

doi:10.2197/ipsjtsldm.8.12

Cited by 22 publications

(7 citation statements)

References 96 publications

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“…An HLS was used to identify the multi‐dimensional design space and obtain the low‐power executions. An in‐depth coverage of HLS low‐power optimization method and synthesis algorithms was introduced in the work of Zhang et al 16 However, optimization process was not carried out in efficient manner.…”

Section: Related Workmentioning

confidence: 99%

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

Rani

Kumar²

2019

Concurrency and Computation

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Summary Very‐large‐scale integration (VLSI) is a procedure of designing integrated circuit (IC) by linking number of transistors into single chip where attaining the higher accuracy is difficult task because of variation in process‐voltage‐temperature (PVT). This work presents Stochastic Spider Monkey Optimization–based High‐Level Synthesis (SSMO‐HLS) Model to improve the performance with better runtime adaptability. In SSMO‐HLS model, behavioral input is collected and dataflow analysis is carried out to convert input into dataflow diagram (DFD). Then, compilation process detects error functional unit (FU) in DFD. Spider monkey optimization is carried out to find optimal functional unit for performing allocation, scheduling, and binding process. After binding, output circuit gets generated with better runtime adaptability in case of PVT variations. The performance of SSMO‐HLS model is carried out using ISCAS'89 Benchmark Dataset where designed model increases FU selection accuracy and reduces error rate and circuit adaptability time when compared to state‐of‐the‐art works.

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Section: Related Workmentioning

confidence: 99%

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

Rani

Kumar²

2019

Concurrency and Computation

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“…However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system level. This is because; system architects have little or no visibility of the lower-level details that are needed to implement low power schemes at RTL [Zhang 2015]. Similarly, a digital backend designer needs to interact intensively with the system architect as well as with the verification team to formulate an appropriate hardware platform and a low power scheme in order to meet the requirements.…”

Section: Low Power Design Flowmentioning

confidence: 99%

“…The authors advocate the use of a system-level solution early in the design cycle for data-flow dominated blocks and their associated memories. Zhang et al [2015] argues that in order to meet strict power requirements, modern day designers may still have to perform manual optimizations on an RTL design described using Verilog or VHDL by applying numerous low power techniques considering functional, structural, temporal and spatial information together. It is extremely difficult to achieve these goals manually in such a complex multidimensional space within a limited time.…”

Section: Related Workmentioning

confidence: 99%

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Qamar

Muslim

Iqbal

et al. 2017

Microprocessors and Microsystems

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The abstraction level for digital designs is rising from Register Transfer Level (RTL) to algorithmic untimed or transaction-based, followed by an automated high level synthesis (HLS) flow. However, it is still a significant challenge for chip architects and designers to describe low-power design decisions at the system level. Nowadays, low power design techniques for digital blocks are applied at RTL and there exists no commercial tool or methodology that can automatically derive the power intent from the system level description. The process requires considerable amount of human intervention and various lower-level details that are needed to implement low power schemes at RTL. This research aims to integrate low power techniques, specifically Power Shut-Off (PSO), within a model based hardware flow and to derive an automated Low Power-High Level Synthesis (LP-HLS) methodology. The methodology aims at minimizing the design effort for low power design by deriving low-level power intent automatically for model-based designs, while using high level synthesis to achieve a broad set of target system implementations. All the information that is needed to implement low power techniques is automatically derived from the systemlevel design using a set of pragmas and a directives file. To illustrate the methodology, three model designs, ranging from simple designs to medium complexity hardware accelerators, are considered. Finally, the power saving results for the design scenarios validate the effectiveness of our LP-HLS methodology. • Hardware~Best practices for EDA • Hardware~Software tools for EDA • Hardware~Hardware description languages and compilation • Hardware~Modeling and parameter extractionAdditional Key Words and Phrases: Hardware accelerators, HLS, RTL, design space exploration, common power format, low power designs, design automation.

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“…HLS has previously explored low‐power design for control‐flow intensive and data‐dominated circuits, and activity reduction [38]. However, HLS for ultra‐low power IoT designs requires automated application of clock‐gating, power gating and DVFS technologies.…”

Section: Custom Platformsmentioning

confidence: 99%

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Chen

Cong

Gurumani

et al. 2016

IET cyber-phys. syst.

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The rise of the Internet of Things has led to an explosion of new sensor computing platforms. The complexity and application domains of IoT devices range from simple self-monitoring devices in vending machines to complex interactive devices with artificial intelligence in smart vehicles and drones. As IoT developers wish to meet more aggressive platform objectives and protect market share through feature differentiation, they must choose between low-cost, and lowperformance CPU-based commercial-off-the-shelf (COTS) systems, and high-performance custom platforms with hardware accelerators such as GPU and FPGA. Both COTS and custom platform designs introduce a variety of design challenges-the extreme pressures on time-to-market, design cost, and development risk are also driving a voracious demand for new CAD technologies to enable rapid, low cost design of effective IoT platforms with smaller design teams and lower risk. In this article, we present a generic IoT device design flow and discuss platform choices available for IoT devices to efficiently tradeoff cost, power, performance and volume constraints: CPUbased systems, and custom platforms that contain hardware accelerators such as FPGA and embedded GPUs. We demonstrate this design process through a driving application in computer vision. We also present current critical design automation needs for IoT development and demonstrate how our prior work in CAD for FPGAs and SoCs begin to address these needs.

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High-level Synthesis for Low-power Design

Cited by 22 publications

References 96 publications

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

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