Scheduling periodic task systems to minimize output jitter

Baruah, Sanjoy; Buttazzo, Giorgio; Gorinsky, Sergey; Lipari, Giuseppe

doi:10.1109/rtcsa.1999.811194

Cited by 66 publications

(48 citation statements)

References 7 publications

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“…To cope with overloads, specific extensions have been proposed in the literature, both for aperiodic (Buttazzo and Stankovic, 1995) and periodic (Koren and Shasha, 1995) load. Also a method for jitter control under EDF has been addressed in Baruah et al (1999) and can be adopted whenever needed.…”

Section: Discussionmentioning

confidence: 99%

Rate Monotonic vs. EDF: Judgment Day

Buttazzo

2003

Embedded Software

121

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Abstract. Since the first results published in 1973 by Liu and Layland on the Rate Monotonic (RM) and Earliest Deadline First (EDF) algorithms, a lot of progress has been made in the schedulability analysis of periodic task sets. Unfortunately, many misconceptions still exist about the properties of these two scheduling methods, which usually tend to favor RM more than EDF. Typical wrong statements often heard in technical conferences and even in research papers claim that RM is easier to analyze than EDF, it introduces less runtime overhead, it is more predictable in overload conditions, and causes less jitter in task execution.Since the above statements are either wrong, or not precise, it is time to clarify these issues in a systematic fashion, because the use of EDF allows a better exploitation of the available resources and significantly improves system's performance. This paper compares RM against EDF under several aspects, using existing theoretical results, specific simulation experiments, or simple counterexamples to show that many common beliefs are either false or only restricted to specific situations.

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Section: Discussionmentioning

confidence: 99%

Rate Monotonic vs. EDF: Judgment Day

Buttazzo

2003

Embedded Software

121

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“…Minimizing the output jitter is a very important issue in control systems (Cervin, 1999). In Baruah et al (1999) a method to reduce the output jitter is presented, consisting in reducing as much as it is possible the relative deadlines of the tasks without violating the feasibility of the task set. However, in Baruah's work tasks are considered synchronous.…”

Section: Discussionmentioning

confidence: 99%

Feasibility Analysis of Real-Time Periodic Tasks with Offsets

Pellizzoni

Lipari

2005

Real-Time Syst

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Abstract. The problem of feasibility analysis of asynchronous periodic task sets, where tasks can have an initial offset, is known to be co-NP-complete in the strong sense. A sufficient pseudo-polynomial test has been proposed by Baruah, Howell and Rosier, which consists in analyzing the feasibility of the corresponding synchronous task set (i.e. all offsets are set equal to 0). If the test gives a positive result, then the original asynchronous task set is feasible; else, no definitive answer can be given. In many cases, this sufficient test is too pessimistic, i.e. it gives no response for many feasible task sets.In this paper, we present a new sufficient pseudo-polynomial test for asynchronous periodic task sets. Our test reduces the pessimism by explicitely considering the offsets in deriving a small set of critical arrival patterns. We show, trough a set of extensive simulations, that our test outperforms the previous sufficient test.

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“…In distributed real-time systems that consist o f various nodes and a communication network connecting the various systems, jitter problem can arise from, such as, delay in network caused by a route consisting o f several hops (Baruah et al, 1999), network protocol (e.g. Ethernet, Computer Area Network (CAN)) (Tindell and Bums, 1994), and the variations in message transmission times (Nolte et al, 2002).…”

Section: Sources Of Jittermentioning

confidence: 99%

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

Phatrapornnant

Pont

2006

IEEE Trans. Comput.

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All rights reserved INFORMATION TO ALL U SE R S The quality of this reproduction is d ep endent upon the quality of the copy submitted.In the unlikely event that the author did not sen d a com plete manuscript and there are m issing p a g es, th e se will be noted. Also, if material had to be removed, a note will indicate the deletion. AbstractThis thesis is concerned with the development o f single-processor embedded systems in which there are requirements for both low CPU energy consumption and low levels of task jitter. The focus o f the work is on ways in which dynamic voltage scaling (DVS) techniques can be incorporated in simple time-triggered scheduling algorithms in order to meet these constraints.Following a review o f previous work in this area, a presentation is made which illustrates the impact o f a naive application o f DVS in a system incorporating a timetriggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) are then introduced which more successfully integrate TTC and DVS techniques. These algorithms involve: (i) changes to system timer settings when the frequency is altered; (ii) use o f a form o f "sandwich delay" to reduce the impact o f changes to the scheduler overhead which arise as a result o f frequency changes, and (iii) execution of jitter-sensitive tasks at a fixed operating frequency.The impact o f these algorithms on both jitter and energy consumption is illustrated empirically on a representative hardware platform, using both "dummy" task sets and a more realistic case study.In designs for which low jitter is an important consideration, at least a limited degree of task pre-emption may be required. A simple time-triggered hybrid (TTH) sched uler can be used to achieve such behaviour. A novel TTH scheduling algorithm (TTH-jDVS) is presented and evaluated, again through use o f dummy task sets and a case study.The third piece o f experimental work presented in this thesis illustrates that -in situations where minimal jitter is required -hardware support is required. To illus trate the potential o f such an approach a final case study is employed.The thesis concludes by making suggestions for further work in this important area.

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Scheduling periodic task systems to minimize output jitter

Cited by 66 publications

References 7 publications

Rate Monotonic vs. EDF: Judgment Day

Rate Monotonic vs. EDF: Judgment Day

Feasibility Analysis of Real-Time Periodic Tasks with Offsets

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

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