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All rights reserved INFORMATION TO ALL U SE R S The quality of this reproduction is d ep endent upon the quality of the copy submitted.In the unlikely event that the author did not sen d a com plete manuscript and there are m issing p a g es, th e se will be noted. Also, if material had to be removed, a note will indicate the deletion. AbstractThis thesis is concerned with the development o f single-processor embedded systems in which there are requirements for both low CPU energy consumption and low levels of task jitter. The focus o f the work is on ways in which dynamic voltage scaling (DVS) techniques can be incorporated in simple time-triggered scheduling algorithms in order to meet these constraints.Following a review o f previous work in this area, a presentation is made which illustrates the impact o f a naive application o f DVS in a system incorporating a timetriggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) are then introduced which more successfully integrate TTC and DVS techniques. These algorithms involve: (i) changes to system timer settings when the frequency is altered; (ii) use o f a form o f "sandwich delay" to reduce the impact o f changes to the scheduler overhead which arise as a result o f frequency changes, and (iii) execution of jitter-sensitive tasks at a fixed operating frequency.The impact o f these algorithms on both jitter and energy consumption is illustrated empirically on a representative hardware platform, using both "dummy" task sets and a more realistic case study.In designs for which low jitter is an important consideration, at least a limited degree of task pre-emption may be required. A simple time-triggered hybrid (TTH) sched uler can be used to achieve such behaviour. A novel TTH scheduling algorithm (TTH-jDVS) is presented and evaluated, again through use o f dummy task sets and a case study.The third piece o f experimental work presented in this thesis illustrates that -in situations where minimal jitter is required -hardware support is required. To illus trate the potential o f such an approach a final case study is employed.The thesis concludes by making suggestions for further work in this important area.

This paper describes a novel two-stage search technique which is intended to support the configuration of timetriggered schedulers for use with resource-constrained embedded systems which employ a single processor. Our overall goal is to identify a scheduler implementation which will ensure that: (i) all task constraints are met; (ii) CPU power consumption is "as low as possible"; (iii) a fully cooperative scheduler architecture is employed whenever possible. Our search process is not exhaustive, and might be described as "best characteristics first" approach. We proceed iteratively, stopping the search when we have identified the first workable solution. We assume thatbecause we have begun the search with "best characteristics"any schedule identified will represent a good (but not necessarily completely optimal) solution. We show that the proposed configuration algorithm is highly effective. We also demonstrate that the algorithm has much lower complexity than alternative "branch and bound" search schemes. We conclude by making some suggestions for future work in this area.