Scheduling and hardware sharing in pipelined data paths

Hwang, Ki Soo; Casavant, Albert E.; Chang, Ching-Tang; d'Abreu, M.

doi:10.1109/iccad.1989.76897

Cited by 72 publications

(21 citation statements)

References 7 publications

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“…Pipelining is an effective method to optimize the execution of a loop with or without loop carried dependencies, especially for DSP [8]. Highly concurrent implementations can be obtained by overlapping the execution of consecutive iterations.…”

Section: Pipeline Synthesis and Optimization: Backgroundmentioning

confidence: 99%

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Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Rahman

Prihozhy

Mattavelli

2011

J Image Video Proc.

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This article describes a pipeline synthesis and optimization technique that increases data throughput of FPGAbased system using minimum pipeline resources. The technique is applied on CAL dataflow language, and designed based on relations, matrices, and graphs. First, the initial as-soon-as-possible (ASAP) and as-late-aspossible (ALAP) schedules, and the corresponding mobility of operators are generated. From this, operator coloring technique is used on conflict and nonconflict directed graphs using recursive functions and explicit stack mechanisms. For each feasible number of pipeline stages, a pipeline schedule with minimum total register width is taken as an optimal coloring, which is then automatically transformed to a description in CAL. The generated pipelined CAL descriptions are finally synthesized to hardware description languages for FPGA implementation. Experimental results of three video processing applications demonstrate up to 3.9× higher throughput for pipelined compared to non-pipelined implementations, and average total pipeline register width reduction of up to 39.6 and 49.9% between the optimal, and ASAP and ALAP pipeline schedules, respectively.

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Section: Pipeline Synthesis and Optimization: Backgroundmentioning

confidence: 99%

“…Sehwa minimizes time delay using a modified list scheduling algorithm with a resource allocation table. HAL [7] performs a time-constrained, functional pipelining scheduling using the force directed method which is modified in [8]. The loop winding method was proposed in the Elf [9] system.…”

Section: Pipeline Synthesis and Optimization: Backgroundmentioning

confidence: 99%

Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Rahman

Prihozhy

Mattavelli

2011

J Image Video Proc.

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“…A graph partitioning technique for scheduling a pipelined data path was presented in [23]. The force-directed scheduling algorithm has also been adapted to solve the same problem in [3], [21].…”

Section: Considerations In Data-path Synthesismentioning

confidence: 99%

“…The operations not on the critical path are assigned one at a time according to their degree of freedom. In force-directed scheduling [3], [21], "force" values are calculated for all operations at all feasible control steps. The pairing of operation and control step that has the most attractive force is selected and assigned.…”

Section: Basic Scheduling Techniquesmentioning

confidence: 99%

A formal approach to the scheduling problem in high level synthesis

Hwang

Lee

Hsu

1991

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

352

111

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“…Many efforts in high-level scheduling have been concentrated on improving circuit performance (time required to execute all the behavioural description operations) by minimizing the slack times wasted in clock cycles. Traditionally, pipelining has been the preferred technique to improve system performance, although it does not reduce the circuit latency [1][2]. In order to reduce the latency, some algorithms have added some optimization phases after the scheduling process to adjust either the number or duration of the clock cycles [3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%